February 1999
54ACT825
8-Bit D Flip-Flop
General Description
The 'ACT825 is an 8-bit buffered register. They have Clock Enable and Clear features which are ideal for parity bus interfacing in high performance microprogramming systems. Also included are multiple enables that allow multi-use control of the interface. The 'ACT825 has noninverting outputs and is fully compatible with AMD's Am29825.
Features
nOutputs source/sink 24 mA
nInputs and outputs are on opposite sides
n'ACT825 has TTL-compatible inputs
nStandard Microcircuit Drawing (SMD)
Ð'ACT825: 5962-91611
Logic Symbols
IEEE/IEC
DS100254-1
DS100254-3
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Pin Names |
Description |
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D0±D7 |
Data Inputs |
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O0±O7 |
Data Outputs |
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2, |
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3 |
Output Enables |
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OE |
1, |
OE |
OE |
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Clock Enable |
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EN |
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Clear |
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CLR |
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CP |
Clock Input |
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FACT™ is a trademark of Fairchild Semiconductor.
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
Flop-Flip D Bit-8 54ACT825
© 1999 National Semiconductor Corporation |
DS100254 |
www.national.com |
Connection Diagrams
Pin Assignment |
Pin Assignment for LCC |
for DIP and Flatpak |
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DS100254-2
Functional Description
The 'ACT825 consists of eight D-type edge-triggered flip-flops. These devices have TRI-STATE® outputs for bus systems, organized in a broadside pinning. In addition to the clock and output enable pins, the buffered clock (CP) and buffered Output Enable (OE) are common to all flip-flops. The flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH CP transition. With OE1, OE2 and OE3 LOW, the contents of the flip-flops are available at the outputs. When one of OE1, OE2 or OE3 is HIGH, the outputs go to the high impedance state.
DS100254-4
Operation of the OE input does not affect the state of the flip-flops. The 'ACT825 has Clear (CLR) and Clock Enable (EN) pins. These pins are ideal for parity bus interfacing in high performance systems.
When CLR is LOW and OE is LOW, the outputs are LOW. When CLR is HIGH, data can be entered into the flip-flops. When EN is LOW, data on the inputs is transferred to the outputs on the LOW-to-HIGH clock transition. When EN is HIGH, the outputs do not change state, regardless of the data or clock input transitions.
Function Table
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Inputs |
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Internal |
Output |
Function |
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CP |
Dn |
Q |
O |
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OE |
CLR |
EN |
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H |
X |
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L |
N |
L |
L |
Z |
High-Z |
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H |
X |
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L |
N |
H |
H |
Z |
High-Z |
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H |
L |
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X |
X |
X |
L |
Z |
Clear |
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L |
L |
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X |
X |
X |
L |
L |
Clear |
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H |
H |
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H |
X |
X |
NC |
Z |
Hold |
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L |
H |
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H |
X |
X |
NC |
NC |
Hold |
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H |
H |
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L |
N |
L |
L |
Z |
Load |
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H |
H |
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L |
N |
H |
H |
Z |
Load |
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L |
H |
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L |
N |
L |
L |
L |
Load |
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L |
H |
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L |
N |
H |
H |
H |
Load |
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H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
N = LOW-to-HIGH Transition
NC = No Change
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Logic Diagram
DS100254-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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