July 1998
54ABT273
Octal D-Type Flip-Flop
General Description
The 'ABT273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's Q output.
All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements.
nBuffered common clock
nBuffered, asynchronous Master Reset
nSee 'ABT377 for clock enable version
nSee 'ABT373 for transparent latch version
nSee 'ABT374 for TRI-STATE® version
nOutput sink capability of 48 mA, source capability of 24 mA
nGuaranteed latchup protection
nHigh impedance glitch free bus loading during entire power up and power down cycle
nNon-destructive hot insertion capability
nDisable time less than enable time to avoid bus contention
nStandard Microcircuit Drawing (SMD) 5962-9321701
Features
n Eight edge-triggered D flip-flops
Ordering Code
Military |
Package |
Package Description |
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Number |
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54ABT273J-QML |
J20A |
20-Lead Ceramic Dual-In-Line |
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54ABT273W-QML |
W20A |
20-Lead Cerpack |
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54ABT273E-QML |
E20A |
20-Lead Ceramic Leadless Chip Carrier, Type C |
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TRI-STATE® is a registered trademark of National Semiconductor Corporation.
Flop-Flip Type-D Octal 54ABT273
© 1998 National Semiconductor Corporation |
DS100205 |
www.national.com |
Connection Diagrams
Pin Assignment for DIP |
Pin Assignment |
and Flatpack |
for LCC |
DS100205-2
DS100205-1
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Pin |
Description |
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Names |
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D0±D7 |
Data Inputs |
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Master Reset |
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MR |
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(Active LOW) |
CP |
Clock Pulse Input |
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(Active Rising Edge) |
Q0±Q7 |
Data Outputs |
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Truth Table
Mode Select-Function Table
Operating Mode |
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Inputs |
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Output |
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MR |
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CP |
Dn |
Qn |
Reset (Clear) |
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L |
X |
X |
L |
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Load ª1º |
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H |
N |
h |
H |
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Load ª0º |
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H |
N |
l |
L |
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H = HIGH Voltage Level steady state
h = HIGH Voltage Level one setup time prior to the LOW-to-HIGH clock transition
L = LOW Voltage Level steady state
I = LOW Voltage Level one setup time prior to the LOW-to-HIGH clock transition
X = Immaterial
N = LOW-to-HIGH clock transition
Logic Diagram
DS100205-3
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2 |
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.
Storage Temperature |
−65ÊC to +150ÊC |
Ambient Temperature under Bias |
−55ÊC to +125ÊC |
Junction Temperature under Bias |
|
Ceramic |
−55ÊC to +175ÊC |
VCC Pin Potential to |
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Ground Pin |
−0.5V to +7.0V |
Input Voltage (Note 2) |
−0.5V to +7.0V |
Input Current (Note 2) |
−30 mA to +5.0 mA |
Voltage Applied to Any Output |
|
in the Disabled or |
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Power-Off State |
−0.5V to +4.75V |
in the HIGH State |
−0.5V to V CC |
Current Applied to Output |
|
in LOW State (Max) |
twice the rated IOL (mA) |
DC Latchup Source Current |
−500 mA |
(Across Comm Operating Range) |
|
Over Voltage Latchup |
VCC + 4.5V |
Recommended Operating
Conditions
Free Air Ambient Temperature |
|
Military |
−55ÊC to +125ÊC |
Supply Voltage |
|
Military |
+4.5V to +5.5V |
Minimum Input Edge Rate |
( V/ t) |
Data Input |
50 mV/ns |
Enable Input |
20 mV/ns |
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
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Symbol |
Parameter |
|
ABT273 |
Units |
VCC |
Conditions |
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Min |
Typ Max |
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VIH |
Input HIGH Voltage |
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2.0 |
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V |
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Recognized HIGH Signal |
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VIL |
Input LOW Voltage |
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0.8 |
V |
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Recognized LOW Signal |
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VCD |
Input Clamp Diode Voltage |
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−1.2 |
V |
Min |
I IN = −18 mA |
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VOH |
Output HIGH Voltage |
54ABT |
2.5 |
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IOH = −3 mA |
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54ABT |
2.0 |
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V |
Min |
IOH = −24 mA |
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VOL |
Output LOW Voltage |
54ABT |
|
0.55 |
V |
Min |
IOL = 48 mA |
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IIH |
Input HIGH Current |
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5 |
µA |
Max |
VIN = 2.7V (Note 4) |
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5 |
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VIN = VCC |
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IBVI |
Input HIGH Current |
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7 |
µA |
Max |
VIN = 7.0V |
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Breakdown Test |
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IIL |
Input LOW Current |
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−5 |
µA |
Max |
V IN = 0.5V (Note 4) |
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−5 |
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V IN = 0.0V |
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VID |
Input Leakage Test |
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4.75 |
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V |
0.0 |
IID = 1.9 µA |
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All Other Pins Grounded |
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IOS |
Output Short-Circuit Current |
−100 |
−275 |
mA |
Max |
V OUT = 0.0V |
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ICEX |
Output High Leakage Current |
|
50 |
µA |
Max |
VOUT = VCC |
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ICCH |
Power Supply Current |
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50 |
µA |
Max |
All Outputs HIGH |
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ICCL |
Power Supply Current |
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30 |
mA |
Max |
All Outputs LOW |
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ICCT |
Maximum ICC/Input |
Outputs Enabled |
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VI = VCC − 2.1V |
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1.5 |
mA |
Max |
Data Input VI = VCC − 2.1V |
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All Others at VCC or GND |
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ICCD |
Dynamic ICC |
No Load |
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0.3 |
mA/ |
Max |
Outputs Open (Note 3) |
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MHz |
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One Bit Toggling, 50% Duty Cycle |
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Note 3: For 8 bits toggling, ICCD < 0.5 mA/MHz.
Note 4: Guaranteed but not tested.
3 |
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