NSC 5962-8769701SRA, 5962-8769701SSA, 5962-8769701S2A, 5962-8769701MSA, 5962-8769701MRA Datasheet
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February 1999
54AC377 · 54ACT377
Octal D Flip-Flop with Clock Enable
General Description
The 'AC/'ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW.
The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's Q output. The CE input must be stable only one setup time prior to the LOW-to-HIGH clock transition for predictable operation.
Features
n ICC reduced by 50%
nIdeal for addressable register applications
nClock enable for address and data synchronization applications
nEight edge-triggered D flip-flops
nBuffered common clock
nOutputs source/sink 24 mA
nSee '273 for master reset version
nSee '373 for transparent latch version
nSee '374 for TRI-STATE® version
n'ACT377 has TTL-compatible inputs
nStandard Microcircuit Drawing (SMD)
Ð'AC377: 5962-88702
Ð'ACT377: 5962-87697
Logic Symbols
IEEE/IEC
DS100290-1
DS100290-2
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Pin |
Description |
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Names |
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D0±D7 |
Data Inputs |
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Clock Enable (Active LOW) |
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CE |
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Q0±Q7 |
Data Outputs |
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CP |
Clock Pulse Input |
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TRI-STATE® is a registered trademark of National Semiconductor Corporation.
FACT® is a registered trademark of Fairchild Semiconductor Corporation.
Enable Clock with Flop-Flip D Octal 54ACT377 · 54AC377
© 1999 National Semiconductor Corporation |
DS100290 |
www.national.com |
Connection Diagrams
Pin Assignment |
Pin Assignment |
for DIP and Flatpak |
for LCC |
DS100290-4
DS100290-3
Mode Select-Function Table
Operating Mode |
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Inputs |
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Outputs |
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CP |
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Dn |
Qn |
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CE |
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Load `1' |
N |
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L |
H |
H |
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Load `0' |
N |
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L |
L |
L |
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Hold (Do Nothing) |
N |
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H |
X |
No Change |
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X |
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H |
X |
No Change |
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H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
N = LOW-to-HIGH Clock Transition
Logic Diagram
DS100290-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2 |
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.
Supply Voltage (VCC) |
−0.5V to +7.0V |
DC Input Diode Current (IIK) |
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VI = −0.5V |
−20 mA |
VI = VCC + 0.5V |
+20 mA |
DC Input Voltage (VI) |
−0.5V to V CC + 0.5V |
DC Output Diode Current (IOK) |
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VO = −0.5V |
−20 mA |
VO = VCC + 0.5V |
+20 mA |
DC Output Voltage (VO) |
−0.5V to V CC + 0.5V |
DC Output Source |
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or Sink Current (IO) |
±50 mA |
DC VCC or Ground Current |
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per Output Pin (ICC or IGND) |
±50 mA |
Storage Temperature (TSTG) |
−65ÊC to +150ÊC |
Junction Temperature (TJ) |
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CDIP |
175ÊC |
Recommended Operating
Conditions
Supply Voltage (VCC) |
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'AC |
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2.0V to 6.0V |
'ACT |
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4.5V to 5.5V |
Input Voltage (VI) |
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0V to VCC |
Output Voltage (VO) |
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0V to VCC |
Operating Temperature (TA) |
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54AC/ACT |
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−55ÊC to +125ÊC |
Minimum Input Edge Rate ( |
V/ |
t) |
'AC Devices |
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VIN from 30% to 70% of VCC |
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VCC @ 3.3V, 4.5V, 5.5V |
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125 mV/ns |
Minimum Input Edge Rate ( |
V/ |
t) |
'ACT Devices |
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VIN from 0.8V to 2.0V |
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VCC @ 4.5V, 5.5V |
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125 mV/ns |
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of FACT® circuits outside databook specifications.
Note 2: See individual datasheets for those devices which differ from the typical input rise and fall times noted here.
DC Characteristics for 'AC Family Devices
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54AC |
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Symbol |
Parameter |
VCC |
TA = |
Units |
Conditions |
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(V) |
−55ÊC to +125ÊC |
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Guaranteed Limits |
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VIH |
Minimum High Level |
3.0 |
2.1 |
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VOUT = 0.1V |
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Input Voltage |
4.5 |
3.15 |
V |
or VCC − 0.1V |
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5.5 |
3.85 |
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VIL |
Maximum Low Level |
3.0 |
0.9 |
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VOUT = 0.1V |
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Input Voltage |
4.5 |
1.35 |
V |
or VCC − 0.1V |
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5.5 |
1.65 |
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VOH |
Minimum High Level |
3.0 |
2.9 |
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IOUT = −50 µA |
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Output Voltage |
4.5 |
4.4 |
V |
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5.5 |
5.4 |
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(Note 3) |
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VIN = VIL or VIH |
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3.0 |
2.4 |
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IOH = −12 mA |
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4.5 |
3.7 |
V |
IOH = −24 mA |
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5.5 |
4.7 |
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IOH = −24 mA |
VOL |
Maximum Low Level |
3.0 |
0.1 |
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IOUT = 50 µA |
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Output Voltage |
4.5 |
0.1 |
V |
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5.5 |
0.1 |
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(Note 3) |
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VIN = VIL or VIH |
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3.0 |
0.50 |
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IOL = 12 mA |
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4.5 |
0.50 |
V |
IOL = 24 mA |
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5.5 |
0.50 |
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IOL = 24 mA |
IIN |
Maximum Input |
5.5 |
±1.0 |
µA |
VI = VCC, GND |
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Leakage Current |
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3 |
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