July 1999
ADC0816/ADC0817
8-Bit µP Compatible A/D Converters
with 16-Channel Multiplexer
General Description
The ADC0816, ADC0817 data acquisition component is a monolithic CMOS device with an 8-bit analog-to-digital converter, 16-channel multiplexer and microprocessor compatible control logic. The 8-bit A/D converter uses successive approximation as the conversion technique. The converter features a high impedance chopper stabilized comparator, a 256R voltage divider with analog switch tree and a successive approximation register. The 16-channel multiplexer can directly access any one of 16-single-ended analog signals, and provides the logic for additional channel expansion. Signal conditioning of any analog input signal is eased by direct access to the multiplexer output, and to the input of the 8-bit A/D converter.
The device eliminates the need for external zero and full-scale adjustments. Easy interfacing to microprocessors is provided by the latched and decoded multiplexer address inputs and latched TTL TRI-STATE® outputs.
The design of the ADC0816, ADC0817 has been optimized by incorporating the most desirable aspects of several A/D conversion techniques. The ADC0816, ADC0817 offers high speed, high accuracy, minimal temperature dependence, excellent long-term accuracy and repeatability, and consumes minimal power. These features make this device ideally suited to applications from process and machine control to consumer and automotive applications. For similar performance in an 8-channel, 28-pin, 8-bit A/D converter, see the ADC0808, ADC0809 data sheet. (See AN-258 for more information.)
Features
nEasy interface to all microprocessors
nOperates ratiometrically or with 5 VDC or analog span adjusted voltage reference
n16-channel multiplexer with latched control logic
nOutputs meet TTL voltage level specifications
n0V to 5V analog input voltage range with single 5V supply
nNo zero or full-scale adjust required
nStandard hermetic or molded 40-pin DIP package
nTemperature range −40ÊC to +85ÊC or −55ÊC to +125ÊC
nLatched TRI-STATE output
nDirect access to ªcomparator inº and ªmultiplexer outº for signal conditioning
nADC0816 equivalent to MM74C948
nADC0817 equivalent to MM74C948-1
Key Specifications
n Resolution |
8 Bits |
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n Total Unadjusted Error |
±1¤2 LSB and ±1 LSB |
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n Single Supply |
5 VDC |
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Low Power |
15 mW |
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Conversion Time |
100 µs |
Block Diagram
DS005277-1
Multiplexer Channel-16 with Converters A/D Compatible µP Bit-8 ADC0816/ADC0817
© 2001 National Semiconductor Corporation |
DS005277 |
www.national.com |
ADC0816/ADC0817
Connection Diagram
Dual-In-Line Package
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DS005277-6 |
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Order Number ADC0816CCN or ADC0817CCN |
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See NS Package Number N40A |
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Ordering Information |
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TEMPERATURE RANGE |
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−40ÊC to +85ÊC |
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Error |
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±1¤2 Bit Unadjusted |
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ADC0816CCN |
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ADC0816CCJ |
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±1 Bit Unadjusted |
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ADC0817CCN |
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Package Outline |
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N40A Molded DIP |
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J40A Hermetic DIP |
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www.national.com |
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Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.
Supply Voltage (VCC) (Note 3) Voltage at Any Pin
Except Control Inputs
Voltage at Control Inputs −0.3V to 15V (START, OE, CLOCK, ALE, EXPANSION CONTROL, ADD A, ADD B, ADD C, ADD D)
Storage Temperature Range Package Dissipation at TA = 25ÊC
Lead Temp. (Soldering, 10 seconds) |
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Dual-In-Line Package (Plastic) |
260ÊC |
Molded Chip Carrier Package |
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Vapor Phase (60 seconds) |
215ÊC |
Infrared (15 seconds) |
220ÊC |
ESD Susceptibility (Note 9) |
400V |
Operating Conditions (Notes 1, 2)
Temperature Range (Note 1) ADC0816CCN, ADC0817CCN
Range of VCC (Note 1) Voltage at Any Pin
Except Control Inputs
Voltage at Control Inputs 0V to 15V (START, OE, CLOCK, ALE, EXPANSION CONTROL, ADD A, ADD B, ADD C, ADD D)
Electrical Characteristics
Converter Specifications: VCC=5 VDC= VREF(+), VREF(−) =GND, VIN=VCOMPARATOR IN,TMIN≤TMAX and fCLK = 640 kHz unless
otherwise stated.
Symbol |
Parameter |
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Conditions |
Min |
Typ |
Max |
Units |
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ADC0816 |
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Total Unadjusted Error |
25ÊC |
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±1¤2 |
LSB |
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(Note 5) |
T |
to T |
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±3¤4 |
LSB |
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MIN |
MAX |
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ADC0817 |
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Total Unadjusted Error |
0ÊC to 70ÊC |
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±1 |
LSB |
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(Note 5) |
T |
to T |
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±11¤4 |
LSB |
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MIN |
MAX |
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Input Resistance |
From Ref(+) to Ref(−) |
1.0 |
4.5 |
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k Ω |
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Analog Input Voltage Range |
(Note 4) V(+) or V(−) |
GND−0.10 |
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V CC+0.10 |
VDC |
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VREF(+) |
Voltage, Top of Ladder |
Measured at Ref(+) |
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VCC |
VCC+0.1 |
V |
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Voltage, Center of Ladder |
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VCC/2−0.1 |
V CC/2 |
VCC/2+0.1 |
V |
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VREF(−) |
Voltage, Bottom of Ladder |
Measured at Ref(−) |
−0.1 |
0 |
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V |
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Comparator Input Current |
fc=640 kHz, (Note 6) |
−2 |
±0.5 |
2 |
µA |
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Electrical Characteristics
Digital Levels and DC Specifications: ADC0816CCN, ADC0817CCN Ð 4.75V ≤VCC≤5.25V, −40ÊC ≤TA≤+85ÊC unless otherwise noted.
Symbol |
Parameter |
Conditions |
Min |
Typ |
Max |
Units |
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ANALOG MULTIPLEXER |
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RON |
Analog Multiplexer ON |
(Any Selected Channel) |
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Resistance |
TA=25ÊC, RL=10k |
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1.5 |
3 |
kΩ |
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TA=85ÊC |
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6 |
kΩ |
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TA=125ÊC |
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9 |
kΩ |
RON |
ON Resistance Between Any |
(Any Selected Channel) |
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75 |
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Ω |
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2 Channels |
RL=10k |
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IOFF+ |
OFF Channel Leakage Current |
VCC=5V, VIN=5V, |
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TA=25ÊC |
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10 |
200 |
nA |
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TMIN to TMAX |
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1.0 |
µA |
IOFF(−) |
OFF Channel Leakage Current |
VCC=5V, VIN=0, |
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TA=25ÊC |
−200 |
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nA |
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TMIN to TMax |
−1.0 |
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µA |
ADC0816/ADC0817
3 |
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ADC0816/ADC0817
Electrical Characteristics (Continued)
Digital Levels and DC Specifications: ADC0816CCN, ADC0817CCN Ð 4.75V ≤VCC≤5.25V, −40ÊC ≤TA≤+85ÊC unless otherwise noted.
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Parameter |
Conditions |
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Min |
Typ |
Max |
Units |
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CONTROL INPUTS |
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V |
Logical ª1º Input Voltage |
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V −1.5 |
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V |
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IN(1) |
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CC |
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VIN(0) |
Logical ª0º Input Voltage |
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1.5 |
V |
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I |
IN(1) |
Logical ª1º Input Current |
V =15V |
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1.0 |
µA |
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IN |
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(The Control Inputs) |
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IN(0) |
Logical ª0º Input Current |
V =0 |
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−1.0 |
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µA |
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IN |
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(The Control Inputs) |
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ICC |
Supply Current |
fCLK=640 kHz |
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0.3 |
3.0 |
mA |
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DATA OUTPUTS AND EOC (INTERRUPT) |
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V |
Logical ª1º Output Voltage |
I=−360 µA, T |
A |
=85ÊC |
V |
CC |
−0.4 |
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V |
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OUT(1) |
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O |
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IO=−300 µA, T A=125ÊC |
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V |
Logical ª0º Output Voltage |
I=1.6 mA |
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0.45 |
V |
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OUT(0) |
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O |
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V |
Logical ª0º Output Voltage EOC |
I=1.2 mA |
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0.45 |
V |
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OUT(0) |
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O |
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IOUT |
TRI-STATE Output Current |
VO=VCC |
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3.0 |
µA |
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VO=0 |
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−3.0 |
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µA |
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Electrical Characteristics
Timing Specifications: VCC=VREF(+)=5V, VREF(−) =GND, tr=tf=20 ns and TA=25ÊC unless otherwise noted.
Symbol |
Parameter |
Conditions |
Min |
Typ |
Max |
Units |
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tWS |
Minimum Start Pulse Width |
(Figure 5) (Note 7) |
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100 |
200 |
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tWALE |
Minimum ALE Pulse Width |
(Figure 5) |
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100 |
200 |
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ts |
Minimum Address Set-Up Time |
(Figure 5) |
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25 |
50 |
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TH |
Minimum Address Hold Time |
(Figure 5) |
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25 |
50 |
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tD |
Analog MUX Delay Time |
RS=OΩ (Figure 5) |
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1 |
2.5 |
µs |
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from ALE |
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tH1, tH0 |
OE Control to Q Logic State |
CL=50 pF, RL=10k (Figure 8) |
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125 |
250 |
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t1H, t0H |
OE Control to Hi-Z |
CL=10 pF, RL=10k (Figure 8) |
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125 |
250 |
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tC |
Conversion Time |
fc=640 kHz, (Figure 5) (Note 8) |
90 |
100 |
116 |
µs |
fc |
Clock Frequency |
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10 |
640 |
1280 |
kHz |
tEOC |
EOC Delay Time |
(Figure 5) |
0 |
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8+2µs |
Clock |
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Periods |
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CIN |
Input Capacitance |
At Control Inputs |
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10 |
15 |
pF |
COUT |
TRI-STATE Output |
At TRI-STATE Outputs (Note 8) |
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10 |
15 |
pF |
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Capacitance |
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Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions.
Note 2: All voltages are measured with respect to GND, unless otherwise specified.
Note 3: A zener diode exists, internally, from VCC to GND and has a typical breakdown voltage of 7 VDC.
Note 4: Two on-chip diodes are tied to each analog input which will forward conduct for analog input voltages one diode drop below ground or one diode drop greater than the VCC supply. The spec allows 100 mV forward bias of either diode. This means that as long as the analog VIN does not exceed the supply voltage by more than 100 mV, the output code will be correct. To achieve an absolute 0 VDC to 5 VDC input voltage range will therefore require a minimum supply voltage of 4.900 VDC over temperature variations, initial tolerance and loading.
Note 5: Total unadjusted error includes offset, full-scale, and linearity errors. See Figure 3. None of these A/Ds requires a zero or full-scale adjust. However, if an all zero code is desired for an analog input other than 0.0V, or if a narrow full-scale span exists (for example: 0.5V to 4.5V full-scale) the reference voltages can be adjusted to achieve this. See Figure 13.
Note 6: Comparator input current is a bias current into or out of the chopper stabilized comparator. The bias current varies directly with clock frequency and has little temperature dependence (Figure 6). See paragraph 4.0.
Note 7: If start pulse is asynchronous with converter clock or if fc > 640 kHz, the minimum start pulse width is 8 clock periods plus 2 µs. For synchronous operation at fc ≤ 640 kHz take start high within 100 ns of clock going low.
Note 8: The outputs of the data register are updated one clock cycle before the rising edge of EOC.
Note 9: Human body model, 100 pF discharged through a 1.5 kΩ resistor.
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