September 1998
54ACTQ646
Quiet Series Octal Transceiver/Register with 3-STATE
Outputs
General Description
The ACTQ646 consist of registered bus transceiver circuits, with outputs, D-type flip-flops, and control circuitry providing multiplexed transmission of data directly from the input bus or from the internal storage registers. Data on the A or B bus will be loaded into the respective registers on the LOW-to-HIGH transition of the appropriate clock pin (CPAB or CPBA). The four fundamental handling functions available are illustrated in Figures 1, 2, 3, 4.
The ACTQ utilizes FSC Quiet Series technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet Series™ features GTO™ output control and undershoot corrector in addition to a split ground bus for superior performance.
Features
nGuaranteed simultaneous switching noise level and dynamic threshold performance
nIndependent registers for A and B busses
nMultiplexed real-time and stored data transfers
n300 mil slim dual-in-line package
nOutputs source/sink 24 mA
nFaster prop delays than the standard AC/ACT646
n4 kV minimum ESD immunity
nStandard Microcircuit Drawing (SMD) 5962-9219601
Logic Symbols
IEEE/IEC
DS100326-1
DS100326-2
Pin Descriptions
Pin Names |
Description |
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A0±A7 |
Data Register A Inputs |
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Data Register A Outputs |
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B0±B7 |
Data Register B Inputs |
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Data Register B Outputs |
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CPAB, |
Clock Pulse Inputs |
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CPBA |
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SAB, SBA |
Transmit/Receive Inputs |
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GTO™ |
is a trademark of National Semiconductor Corporation |
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FACT™ |
and FACT Quiet Series™ are trademarks of Fairchild Semiconductor Corporation |
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Outputs STATE-3 with Transceiver/Register Octal Series Quiet 54ACTQ646
© 1998 National Semiconductor Corporation |
DS100326 |
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Logic Symbols (Continued)
Pin Descriptions (Continued)
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Pin Names |
Description |
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Output Enable Input |
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G |
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DIR |
Direction Control Input |
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Connection Diagram
Pin Assignment for DIP and Flatpack
DS100326-3
Pin Assignment
for LCC
DS100326-4
www.national.com |
2 |
Real Time Transfer |
Storage from |
A-Bus to B-Bus |
Bus to Register |
DS100326-7
DS100326-5
FIGURE 1. |
FIGURE 3. |
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Real Time Transfer |
Transfer from |
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Register to Bus |
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B-Bus to A-Bus |
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DS100326-8
DS100326-6
FIGURE 4.
FIGURE 2.
Function Table
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Inputs |
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Data I/O (Note 1) |
Function |
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G |
DIR |
CPAB |
CPBA |
SAB |
SBA |
A0±A7 |
B0±B7 |
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H |
X |
H or L |
H or L |
X |
X |
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Isolation |
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H |
X |
N |
X |
X |
X |
Input |
Input |
Clock An Data into A Register |
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H |
X |
X |
N |
X |
X |
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Clock Bn Data into B Register |
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L |
H |
X |
X |
L |
X |
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An to Bn Ð Real Time (Transparent Mode) |
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L |
H |
N |
X |
L |
X |
Input |
Output |
Clock An Data into A Register |
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L |
H |
H or L |
X |
H |
X |
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A Register to Bn (Stored Mode) |
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L |
H |
N |
X |
H |
X |
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Clock An Data into A Register and Output to Bn |
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L |
L |
X |
X |
X |
L |
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Bn to An Ð Real Time (Transparent Mode) |
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L |
L |
X |
N |
X |
L |
Output |
Input |
Clock Bn Data into B Register |
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L |
L |
X |
H or L |
X |
H |
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B Register to An (Stored Mode) |
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L |
L |
X |
N |
X |
H |
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Clock Bn Data into B Register and Output to An |
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
N = LOW-to-HIGH Transition
Note 1: The data output functions may be enabled or disabled by various signals at the G and DIR inputs. Data input functions are always enabled; i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs.
3 |
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