NSC ADC0820BMWC, ADC0820BMDC, ADC0820BCJ, ADC0820CMWC, ADC0820CMDC Datasheet

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June 1999

ADC0820

8-Bit High Speed µP Compatible A/D Converter with

Track/Hold Function

General Description

By using a half-flash conversion technique, the 8-bit ADC0820 CMOS A/D offers a 1.5 µs conversion time and dissipates only 75 mW of power. The half-flash technique consists of 32 comparators, a most significant 4-bit ADC and a least significant 4-bit ADC.

The input to the ADC0820 is tracked and held by the input sampling circuitry eliminating the need for an external sample-and-hold for signals moving at less than 100 mV/µs.

For ease of interface to microprocessors, the ADC0820 has been designed to appear as a memory location or I/O port without the need for external interfacing logic.

Key Specifications

j Resolution	8 Bits
j Conversion Time	2.5 µs Max (RD Mode)
	1.5 µs Max (WR-RD Mode)
j Low Power	75 mW Max
j Total Unadjusted
Error	±1¤2 LSB and ± 1 LSB

Features

nBuilt-in track-and-hold function

nNo missing codes

nNo external clocking

nSingle supply Ð 5 V DC

nEasy interface to all microprocessors, or operates stand-alone

nLatched STRI-STATE output

nLogic inputs and outputs meet both MOS and T2L voltage level specifications

nOperates ratiometrically or with any reference value equal to or less than VCC

n0V to 5V analog input voltage range with single 5V supply

nNo zero or full-scale adjust required

nOverflow output available for cascading

n0.3" standard width 20-pin DIP

n20-pin molded chip carrier package

n20-pin small outline package

n20-pin shrink small outline package (SSOP)

Connection and Functional Diagrams

Dual-In-Line, Small Outline

and SSOP Packages Molded Chip Carrier

Package

DS005501-1	DS005501-33

Top View

Function Track/Hold with Converter A/D Compatible µP Speed High Bit-8 ADC0820

DS005501

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ADC0820

Connection and Functional Diagrams (Continued)

				DS005501-2
			FIGURE 1.
Ordering Information

	Part Number	Total		Package	Temperature
		Unadjusted Error			Range

	ADC0820BCV			V20A Ð Molded Chip Carrier	0ÊC to +70ÊC
	ADC0820BCWM	±1¤2 LSB		M20B Ð Wide Body Small Outline	0ÊC to +70ÊC
	ADC0820BCN			N20A Ð Molded DIP	0ÊC to +70ÊC

	ADC0820CCJ			J20A Ð Cerdip	−40ÊC to +85ÊC
	ADC0820CCWM	±1 LSB		M20B Ð Wide Body Small Outline	0ÊC to +70ÊC
	ADC0820CIWM	±1 LSB		M20B Ð Wide Body Small Outline	−40ÊC to +85ÊC
	ADC0820CIWM			M20B Ð Wide Body Small Outline	−40ÊC to +85ÊC
	ADC0820CCN			N20A Ð Molded DIP	0ÊC to +70ÊC

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Absolute Maximum Ratings (Notes 1, 2)

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.

Supply Voltage (VCC)	10V
Logic Control Inputs	−0.2V to V CC +0.2V
Voltage at Other Inputs and Output	−0.2V to V CC +0.2V
Storage Temperature Range	−65ÊC to +150ÊC
Package Dissipation at TA = 25ÊC	875 mW
Input Current at Any Pin (Note 5)	1 mA
Package Input Current (Note 5)	4 mA
ESD Susceptability (Note 9)	1200V
Lead Temp. (Soldering, 10 sec.)
Dual-In-Line Package (plastic)	260ÊC

Dual-In-Line Package (ceramic)	300ÊC
Surface Mount Package
Vapor Phase (60 sec.)	215ÊC
Infrared (15 sec.)	220ÊC

Operating Ratings (Notes 1, 2)

Temperature Range	TMIN≤TA≤TMAX
ADC0820CCJ	−40ÊC ≤TA≤+85ÊC
ADC0820CIWM	−40ÊC ≤TA≤+85ÊC
ADC0820BCN, ADC0820CCN	0ÊC≤TA≤70ÊC
ADC0820BCV	0ÊC≤TA≤70ÊC
ADC0820BCWM, ADC0820CCWM	0ÊC≤TA≤70ÊC
VCC Range	4.5V to 8V

Converter Characteristics

The following specifications apply for RD mode (pin 7=0), VCC=5V, VREF(+)=5V,and VREF(−)=GND unless otherwise specified.

Boldface limits apply from TMIN to TMAX; all other limits TA=Tj=25ÊC.

Parameter

Conditions

ADC0820BCN, ADC0820CCN

Limit

ADC0820CCJ

ADC0820BCV, ADC0820BCWM

Units

ADC0820CCWM, ADC0820CIWM

Typ

Tested

Design

Typ

Tested

Design

(Note 6)

Limit

(Note 6)

Limit

(Note 7)

(Note 8)

(Note 7)

(Note 8)

Resolution

Bits

Total Unadjusted

ADC0820BCN, BCWM

±1¤2

± 1¤2

LSB

Error

ADC0820CCJ

± 1

LSB

(Note 3)

ADC0820CCN, CCWM, CIWM,

±1

± 1

LSB

ADC0820CCMSA

±1

± 1

LSB

Minimum Reference

2.3

1.00

2.3

1.2

kΩ

Resistance

Maximum Reference

2.3

5.3

kΩ

Resistance

Maximum VREF(+)

VCC

Input Voltage

Minimum VREF(−)

GND

Input Voltage

Minimum VREF(+)

VREF(−)

Input Voltage

Maximum VREF(−)

VREF(+)

Input Voltage

Maximum VIN Input

VCC+0.1

Voltage

Minimum VIN Input

GND−0.1

Voltage

Maximum Analog

=VCC

Input Leakage

VIN=VCC

0.3

µA

Current

VIN=GND

−3

−0.3

−3

µA

Power Supply

VCC=5V±5%

±1/16

± 1¤4

±1/16

±1¤4

± 1¤4

LSB

Sensitivity

ADC0820

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ADC0820

DC Electrical Characteristics

The following specifications apply for VCC=5V, unless otherwise specified. Boldface limits apply from TMIN to TMAX; all other limits TA=TJ=25ÊC.

Parameter

Conditions

ADC0820BCN, ADC0820CCN

Limit

ADC0820CCJ

ADC0820BCV, ADC0820BCWM

Units

ADC0820CCWM, ADC0820CIWM

Typ

Tested

Design

Typ

Tested

Design

(Note 6)

Limit

(Note 6)

Limit

(Note 7)

(Note 8)

(Note 7)

(Note 8)

IN(1)

, Logical ª1º

V =5.25V

2.0

Input Voltage

Mode

3.5

, Logical ª0º

V =4.75V

0.8

IN(0)

Input Voltage

Mode

1.5

, Logical ª1º

=5V;

0.005

µA

IN(1)

Input Current

VIN(1)=5V;

0.1

0.3

µA

VIN(1)=5V; Mode

200

170

200

µA

, Logical ª0º

=0V;

−0.005

−1

−0.005

−1

µA

IN(0)

Input Current

Mode

OUT(1)

, Logical ª1º

V =4.75V, I

OUT

=−360 µA;

2.4

2.8

2.4

Output Voltage

DB0±DB7,

OFL

INT

VCC=4.75V, IOUT=−10 µA;

4.5

4.6

4.5

DB0±DB7,

OFL

INT

OUT(0)

, Logical ª0º

V =4.75V, I

OUT

=1.6 mA;

0.4

0.34

0.4

Output Voltage

DB0±DB7,

, RDY

OFL

INT

IOUT, TRI-STATE

VOUT=5V; DB0±DB7, RDY

0.1

0.3

µA

Output Current

VOUT=0V; DB0±DB7, RDY

−0.1

−3

−0.1

−0.3

−3

µA

ISOURCE, Output

VOUT=0V; DB0±DB7,

−12

−6

−12

−7.2

−6

OFL

Source Current

−9

−4.0

−9

−5.3

−4.0

INT

ISINK, Output Sink

VOUT=5V; DB0±DB7,

8.4

OFL

Current

, RDY

INT

ICC, Supply Current

=WR

=RD =0

7.5

AC Electrical Characteristics

The following specifications apply for VCC=5V, tr=tf=20 ns, VREF(+)=5V, VREF(−)=0V and T A=25ÊC unless otherwise specified.

						Typ	Tested	Design
Parameter					Conditions	(Note 6)	Limit	Limit	Units
							(Note 7)	(Note 8)

tCRD, Conversion Time for RD					Pin 7 = 0, Figure 2	1.6		2.5	µs
Mode

tACC0, Access Time (Delay from					Pin 7 = 0, Figure 2	tCRD+20		tCRD+50	ns

Falling Edge of	RD		to Output
Valid)

tCWR-RD, Conversion Time for					Pin 7 = VCC; tWR = 600 ns,			1.52	µs
WR-RD Mode					tRD=600 ns; Figures 3, 4
tWR, Write Time				Min	Pin 7 = VCC; Figures 3, 4		600		ns
				Max	(Note 4) See Graph	50			µs

tRD, Read Time				Min	Pin 7 = VCC; Figures 3, 4		600		ns
					(Note 4) See Graph

tACC1, Access Time (Delay from					Pin 7 = VCC, tRD<tI; Figure 3
					CL=15 pF
Falling Edge of	RD	to Output			CL=15 pF	190		280	ns
Valid)

					CL=100 pF	210		320	ns

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AC Electrical Characteristics (Continued)

The following specifications apply for VCC=5V, tr=tf=20 ns, VREF(+)=5V, VREF(−)=0V and T A=25ÊC unless otherwise specified.

Typ

Tested

Design

Parameter

Conditions

(Note 6)

Limit

Units

(Note 7)

(Note 8)

tACC2, Access Time (Delay from

Pin 7 = VCC, tRD>tI; Figure 4

Falling Edge of

to Output

CL=15 pF

120

Valid)

CL=100 pF

150

tACC3, Access Time (Delay from

RPULLUP = 1k and CL = 15 pF

Rising Edge of RDY to Output

Valid)

tI, Internal Comparison Time

Pin 7=VCC; Figures 4, 5

800

1300

CL=50 pF

t1H, t0H, TRI-STATE Control

RL=1k, CL=10 pF

100

200

(Delay from Rising Edge of

Hi-Z State)

Pin 7 = VCC, CL= 50 pF

INTL, Delay from Rising Edge of

to Falling Edge of

tRD>tI; Figure 4

INT

tRD<tI; Figure 3

tRD+200

tRD+290

Figures 2, 3, 4

125

225

INTH, Delay from Rising Edge of

to Rising Edge of

CL=50 pFc

INT

Figure 5, CL=50 pF

175

270

INTHWR, Delay from Rising Edge of

to Rising Edge of

INT

tRDY, Delay from

to RDY

Figure 2, CL=50 pF, Pin 7 =0

100

tID, Delay from

INT

to Output Valid

Figure 5

Pin 7=VCC, tRD<tI

tRI, Delay from

INT

200

290

Figure 3

tP, Delay from End of Conversion

Figures 2, 3, 4, 5

500

to Next Conversion

(Note 4) See Graph

Slew Rate, Tracking

0.1

V/µs

CVIN, Analog Input Capacitance

COUT, Logic Output Capacitance

CIN, Logic Input Capacitance

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions.

Note 2: All voltages are measured with respect to the GND pin, unless otherwise specified.

Note 3: Total unadjusted error includes offset, full-scale, and linearity errors.

Note 4: Accuracy may degrade if tWR or tRD is shorter than the minimum value specified. See Accuracy vs tWR and Accuracy vs tRD graphs.

Note 5: When the input voltage (VIN) at any pin exceeds the power supply rails (VIN < V− or VIN > V+) the absolute value of current at that pin should be limited to 1 mA or less. The 4 mA package input current limits the number of pins that can exceed the power supply boundaries with a 1 mA current limit to four.

Note 6: Typicals are at 25ÊC and represent most likely parametric norm.

Note 7: Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level).

Note 8: Design limits are guaranteed but not 100% tested. These limits are not used to calculate outgoing quality levels.

Note 9: Human body model, 100 pF discharaged through a 1.5 kΩ resistor.

ADC0820

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ADC0820

TRI-STATE Test Circuits and Waveforms

t1H

DS005501-4

DS005501-3

tr=20 ns

t0H

DS005501-6

tr=20 ns

DS005501-5

Timing Diagrams

DS005501-7

Note: On power-up the state of INT can be high or low.

FIGURE 2. RD Mode (Pin 7 is Low)

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Timing Diagrams (Continued)

DS005501-8

FIGURE 3. WR-RD Mode (Pin 7 is High and tRD<tI)

DS005501-9

FIGURE 4. WR-RD Mode (Pin 7 is High and tRD>tI)

DS005501-10

FIGURE 5. WR-RD Mode (Pin 7 is High)

Stand-Alone Operation

ADC0820

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