NSC 5962R8752501SCA, 5962R8752501S2A, 5962R8752501BDA, 5962R8752501SDA, 5962-8752501SDA Datasheet
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August 1998
54AC74 · 54ACT74
Dual D-Type Positive Edge-Triggered Flip-Flop
General Description
The 'AC/'ACT74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q, Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. After the Clock Pulse input threshold voltage has been passed, the Data input is locked out and information present will not be transferred to the outputs until the next rising edge of the Clock Pulse input.
Asynchronous Inputs:
LOW input to SD (Set) sets Q to HIGH level
LOW input to CD (Clear) sets Q to LOW level Clear and Set are independent of clock
Simultaneous LOW on CD and SD makes both Q and Q HIGH
Features
nICC reduced by 50%
nOutput source/sink 24 mA
n'ACT74 has TTL-compatible inputs
nStandard Microcircuit Drawing (SMD)
Ð'AC74: 5962-88520
Ð'ACT74: 5962-87525
Logic Symbols
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DS100266-2 |
DS100266-1 |
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Pin Names |
Description |
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IEEE/IEC |
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D1, D2 |
Data Inputs |
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CP1, CP2 |
Clock Pulse Inputs |
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D2 |
Direct Clear Inputs |
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C |
D1, |
C |
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D2 |
Direct Set Inputs |
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S |
D1, |
S |
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Q1, |
Q |
1, Q2, |
Q |
2 |
Outputs |
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DS100266-3
FACT® is a registered trademark of Fairchild Semiconductor Corporation.
Flop-Flip Triggered-Edge Positive Type-D Dual 54ACT74 · 54AC74
© 1998 National Semiconductor Corporation |
DS100266 |
www.national.com |
Connection Diagrams
Pin Assignment for DIP and Flatpak
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DS100266-4 |
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Truth Table |
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(Each Half) |
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Inputs |
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Outputs |
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S |
D |
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C |
D |
CP |
D |
Q |
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Q |
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L |
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H |
X |
X |
H |
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L |
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H |
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L |
X |
X |
L |
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H |
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L |
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L |
X |
X |
H |
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H |
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H |
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H |
N |
H |
H |
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L |
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H |
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H |
N |
L |
L |
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H |
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H |
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H |
L |
X |
Q0 |
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Q |
0 |
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H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
N = LOW-to-HIGH Clock Transition
Q0(Q0) = Previous Q(Q) before LOW-to-HIGH Transition of Clock
Logic Diagram
Pin Assignment for LCC
DS100266-5
DS100266-6
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.national.com |
2 |
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.
Supply Voltage (VCC) |
−0.5V to +7.0V |
DC Input Diode Current (IIK) |
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VI = −0.5V |
−20 mA |
VI = VCC + 0.5V |
+20 mA |
DC Input Voltage (VI) |
−0.5V to V CC + 0.5V |
DC Output Diode Current (IOK) |
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VO = −0.5V |
−20 mA |
VO = VCC + 0.5V |
+20 mA |
DC Output Voltage (VO) |
−0.5V to V CC + 0.5V |
DC Output Source |
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or Sink Current (IO) |
±50 mA |
DC VCC or Ground Current |
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per Output Pin (ICC or IGND) |
±50 mA |
Storage Temperature (TSTG) |
−65ÊC to +150ÊC |
Junction Temperature (TJ) |
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CDIP |
175ÊC |
Recommended Operating
Conditions
Supply Voltage (VCC) |
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'AC |
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2.0V to 6.0V |
'ACT |
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4.5V to 5.5V |
Input Voltage (VI) |
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0V to VCC |
Output Voltage (VO) |
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0V to VCC |
Operating Temperature (TA) |
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54AC/ACT |
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−55ÊC to +125ÊC |
Minimum Input Edge Rate ( |
V/ |
t) |
'AC Devices |
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VIN from 30% to 70% of VCC |
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VCC @ 3.3V, 4.5V, 5.5V |
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125 mV/ns |
Minimum Input Edge Rate ( |
V/ |
t) |
'ACT Devices |
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VIN from 0.8V to 2.0V |
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VCC @ 4.5V, 5.5V |
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125 mV/ns |
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of FACT® circuits outside databook specifications.
DC Characteristics for 'AC Family Devices
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54AC |
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Symbol |
Parameter |
VCC |
TA = |
Units |
Conditions |
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(V) |
−55ÊC to +125ÊC |
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Guaranteed |
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Limits |
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VIH |
Minimum High |
3.0 |
2.1 |
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VOUT = 0.1V |
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Level Input |
4.5 |
3.15 |
V |
or VCC − 0.1V |
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Voltage |
5.5 |
3.85 |
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VIL |
Maximum Low |
3.0 |
0.9 |
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VOUT = 0.1V |
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Level Input |
4.5 |
1.35 |
V |
or VCC − 0.1V |
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Voltage |
5.5 |
1.65 |
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VOH |
Minimum High |
3.0 |
2.9 |
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IOUT = −50 µA |
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Level Output |
4.5 |
4.4 |
V |
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Voltage |
5.5 |
5.4 |
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(Note 2) |
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VIN = VIL or VIH |
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3.0 |
2.4 |
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−12 mA |
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4.5 |
3.7 |
V |
IOH |
−24 mA |
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5.5 |
4.7 |
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−24 mA |
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VOL |
Maximum Low |
3.0 |
0.1 |
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IOUT = 50 µA |
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Level Output |
4.5 |
0.1 |
V |
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Voltage |
5.5 |
0.1 |
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(Note 2) |
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VIN = VIL or VIH |
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3.0 |
0.5 |
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12 mA |
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4.5 |
0.5 |
V |
IOL |
24 mA |
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5.5 |
0.5 |
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24 mA |
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IIN |
Maximum Input |
5.5 |
±1.0 |
µA |
VI = VCC, GND |
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Leakage Current |
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3 |
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