NSC 5962R8968901VFA, 5962R8968901VEA, 5962R8968901V2A, 5962R8968901FA, 5962R8968901EA Datasheet
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July 1998
54AC257 · 54ACT257
Quad 2-Input Multiplexer with TRI-STATE® Outputs
General Description
The 'AC/'ACT257 is a quad 2-input multiplexer with TRI-STATE outputs. Four bits of data from two sources can be selected using a Common Data Select input. The four outputs present the selected data in true (noninverted) form. The outputs may be switched to a high impedance state by placing a logic HIGH on the common Output Enable (OE) input, allowing the outputs to interface directly with bus-oriented systems.
Features
nICC and IOZ reduced by 50%
nMultiplexer expansion by tying outputs together
nNoninverting TRI-STATE outputs
nOutputs source/sink 24 mA
n'ACT257 has TTL-compatible inputs
nStandard Military Drawing (SMD)
Ð'AC257: 5962-88703
Ð'ACT257: 5962-89689
Logic Symbols
IEEE/IEC
DS100286-1
DS100286-2
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Pin Names |
Description |
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S |
Common Data Select Input |
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TRI-STATE Output Enable Input |
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OE |
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I0a±I0d |
Data Inputs from Source 0 |
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I1a±I1d |
Data Inputs from Source 1 |
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Za±Zd |
TRI-STATE Multiplexer Outputs |
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TRI-STATE® is a registered trademark of National Semiconductor Corporation.
FACT™ is a trademark of Fairchild Semiconductor Corporation.
Outputs STATE-TRI with Multiplexer Input-2 Quad 54ACT257 · 54AC257
© 1998 National Semiconductor Corporation |
DS100286 |
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Connection Diagrams
Pin Assignment for
DIP and Flatpak
DS100286-3
Pin Assignment for LCC
DS100286-4
Logic Diagram
Functional Description
The 'AC/'ACT257 is quad 2-input multiplexer with TRI-STATE outputs. It selects four bits of data from two sources under control of a Common Data Select input. When the Select input is LOW, the I0x inputs are selected and when Select is HIGH, the I1x inputs are selected. The data on the selected inputs appears at the outputs in true (noninverted) form. The device is the logic implementation of a 4-pole, 2-position switch where the position of the switch is determined by the logic levels supplied to the Select input. The logic equations for the outputs are shown below:
Za = OE · (11a · S + I0a · S)
Zb = OE · (11b · S + I0b · S)
Zc = OE · (11c · S + I0c · S)
Zd = OE · (11d · S + I0d · S)
When the Output Enable (OE) is HIGH, the outputs are forced to a high impedance state. If the outputs are tied together, all but one device must be in the high impedance state to avoid high currents that would exceed the maximum ratings. Designers should ensure the Output Enable signals to TRI-STATE devices whose outputs are tied together are designed so there is no overlap.
Truth Table
Output |
Select |
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Data |
Outputs |
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Enable |
Input |
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Inputs |
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OE |
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S |
I0 |
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I1 |
Z |
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H |
X |
X |
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X |
Z |
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L |
H |
X |
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L |
L |
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L |
H |
X |
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H |
H |
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L |
L |
L |
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X |
L |
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L |
L |
H |
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X |
H |
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H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
DS100286-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2 |
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.
Supply Voltage (VCC) |
−0.5V to +7.0V |
DC Input Diode Current (IIK) |
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VI = −0.5V |
−20 mA |
VI = VCC +0.5V |
+20 mA |
DC Input Voltage (VI) |
−0.5V to V CC +0.5V |
DC Output Diode Current (IOK) |
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VO = −0.5V |
−20 mA |
VO = VCC +0.5V |
+20 mA |
DC Output Voltage (VO) |
−0.5V to V CC +0.5V |
DC Output Source or Sink Current |
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(IO) |
±50 mA |
DC VCC or Ground Current |
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Per Output Pin (ICC or IGND) |
±50 mA |
Storage Temperature (TSTG) |
−65ÊC to +150ÊC |
Junction Temperature (TJ) |
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CDIP |
175ÊC |
Recommended Operating
Conditions
Supply Voltage (VCC) |
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'AC |
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2.0V to 6.0V |
'ACT |
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4.5V to 5.5V |
Input Voltage (VI) |
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0V to VCC |
Output Voltage (VO) |
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0V to VCC |
Operating Temperature (TA) |
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54AC/ACT |
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−55ÊC to +125ÊC |
Minimum Input Edge Rate ( |
V/ |
t) |
'AC Devices |
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VIN from 30% to 70% of VCC |
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VCC @ 3.3V, 4.5V, 5.5V |
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125 mV/ns |
Minimum Input Edge Rate ( |
V/ |
t) |
'ACT Devices |
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VIN from 0.8V to 2.0V |
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VCC @ 4.5V, 5.5V |
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125 mV/ns |
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of FACT™ circuits outside databook specifications.
DC Characteristics for 'AC Family Devices
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54AC |
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Symbol |
Parameter |
VCC |
TA = |
Units |
Conditions |
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(V) |
−55ÊC to +125ÊC |
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Guaranteed |
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Limits |
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VIH |
Minimum High |
3.0 |
2.1 |
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VOUT = 0.1V |
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Level Input |
4.5 |
3.15 |
V |
or VCC − 0.1V |
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Voltage |
5.5 |
3.85 |
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VIL |
Maximum Low |
3.0 |
0.9 |
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VOUT = 0.1V |
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Level Input |
4.5 |
1.35 |
V |
or VCC − 0.1V |
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Voltage |
5.5 |
1.65 |
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VOH |
Minimum High |
3.0 |
2.9 |
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IOUT = −50 µA |
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Level Output |
4.5 |
4.4 |
V |
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Voltage |
5.5 |
5.4 |
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(Note 2) |
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VIN = VIL or VIH |
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3.0 |
2.4 |
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−12 mA |
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4.5 |
3.7 |
V |
IOH |
−24 mA |
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5.5 |
4.7 |
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−24 mA |
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VOL |
Maximum Low |
3.0 |
0.1 |
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IOUT = 50 µA |
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Level Output |
4.5 |
0.1 |
V |
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Voltage |
5.5 |
0.1 |
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(Note 2) |
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VIN = VIL or VIH |
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3.0 |
0.50 |
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12 mA |
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4.5 |
0.50 |
V |
IOL |
24 mA |
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5.5 |
0.50 |
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24 mA |
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IIN |
Maximum Input |
5.5 |
±1.0 |
µA |
VI = VCC, GND |
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Leakage Current |
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3 |
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