June 1999
ADC0820
8-Bit High Speed µP Compatible A/D Converter with
Track/Hold Function
General Description
By using a half-flash conversion technique, the 8-bit ADC0820 CMOS A/D offers a 1.5 µs conversion time and dissipates only 75 mW of power. The half-flash technique consists of 32 comparators, a most significant 4-bit ADC and a least significant 4-bit ADC.
The input to the ADC0820 is tracked and held by the input sampling circuitry eliminating the need for an external sample-and-hold for signals moving at less than 100 mV/µs.
For ease of interface to microprocessors, the ADC0820 has been designed to appear as a memory location or I/O port without the need for external interfacing logic.
Key Specifications
n Resolution |
8 Bits |
n Conversion Time |
2.5 µs Max (RD Mode) |
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1.5 µs Max (WR-RD Mode) |
n Low Power |
75 mW Max |
n Total Unadjusted |
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Error |
±1¤2 LSB and ± 1 LSB |
Features
nBuilt-in track-and-hold function
nNo missing codes
nNo external clocking
nSingle supply Ð 5 V DC
nEasy interface to all microprocessors, or operates stand-alone
nLatched TRI-STATE® output
nLogic inputs and outputs meet both MOS and T2L voltage level specifications
nOperates ratiometrically or with any reference value equal to or less than VCC
n0V to 5V analog input voltage range with single 5V supply
nNo zero or full-scale adjust required
nOverflow output available for cascading
n0.3" standard width 20-pin DIP
n20-pin molded chip carrier package
n20-pin small outline package
n20-pin shrink small outline package (SSOP)
Connection and Functional Diagrams
Dual-In-Line, Small Outline
and SSOP Packages Molded Chip Carrier
Package
DS005501-1 |
DS005501-33 |
Top View
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
Function Track/Hold with Converter A/D Compatible µP Speed High Bit-8 ADC0820
© 1999 National Semiconductor Corporation |
DS005501 |
www.national.com |
Connection and Functional Diagrams (Continued)
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DS005501-2 |
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FIGURE 1. |
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Ordering Information |
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Part Number |
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Total |
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Package |
Temperature |
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Unadjusted Error |
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Range |
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ADC0820BCV |
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V20A Ð Molded Chip Carrier |
0ÊC to +70ÊC |
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ADC0820BCWM |
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±1¤2 LSB |
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M20B Ð Wide Body Small Outline |
0ÊC to +70ÊC |
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ADC0820BCN |
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N20A Ð Molded DIP |
0ÊC to +70ÊC |
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ADC0820CCJ |
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J20A Ð Cerdip |
−40ÊC to +85ÊC |
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ADC0820CCWM |
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±1 LSB |
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M20B Ð Wide Body Small Outline |
0ÊC to +70ÊC |
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ADC0820CIWM |
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M20B Ð Wide Body Small Outline |
−40ÊC to +85ÊC |
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ADC0820CCN |
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N20A Ð Molded DIP |
0ÊC to +70ÊC |
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www.national.com |
2 |
Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.
Supply Voltage (VCC) |
10V |
Logic Control Inputs |
−0.2V to V CC +0.2V |
Voltage at Other Inputs and Output |
−0.2V to V CC +0.2V |
Storage Temperature Range |
−65ÊC to +150ÊC |
Package Dissipation at TA = 25ÊC |
875 mW |
Input Current at Any Pin (Note 5) |
1 mA |
Package Input Current (Note 5) |
4 mA |
ESD Susceptability (Note 9) |
1200V |
Lead Temp. (Soldering, 10 sec.) |
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Dual-In-Line Package (plastic) |
260ÊC |
Dual-In-Line Package (ceramic) |
300ÊC |
Surface Mount Package |
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Vapor Phase (60 sec.) |
215ÊC |
Infrared (15 sec.) |
220ÊC |
Operating Ratings (Notes 1, 2)
Temperature Range |
TMIN≤TA≤TMAX |
ADC0820CCJ |
−40ÊC ≤TA≤+85ÊC |
ADC0820CIWM |
−40ÊC ≤TA≤+85ÊC |
ADC0820BCN, ADC0820CCN |
0ÊC≤TA≤70ÊC |
ADC0820BCV |
0ÊC≤TA≤70ÊC |
ADC0820BCWM, ADC0820CCWM |
0ÊC≤TA≤70ÊC |
VCC Range |
4.5V to 8V |
Converter Characteristics
The following specifications apply for RD mode (pin 7=0), VCC=5V, VREF(+)=5V,and VREF(−) =GND unless otherwise specified. Boldface limits apply from TMIN to TMAX; all other limits TA=Tj=25ÊC.
Parameter |
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Conditions |
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ADC0820BCN, ADC0820CCN |
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Limit |
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ADC0820CCJ |
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ADC0820BCV, ADC0820BCWM |
Units |
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ADC0820CCWM, ADC0820CIWM |
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Typ |
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Tested |
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Design |
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Tested |
Design |
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(Note 6) |
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Limit |
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Limit |
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Limit |
Limit |
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(Note 7) |
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(Note 8) |
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(Note 7) |
(Note 8) |
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Resolution |
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8 |
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8 |
8 |
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Bits |
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Total Unadjusted |
ADC0820BCN, BCWM |
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±1¤2 |
± 1¤2 |
LSB |
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Error |
ADC0820CCJ |
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± 1 |
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LSB |
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(Note 3) |
ADC0820CCN, CCWM, CIWM, |
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±1 |
± 1 |
LSB |
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ADC0820CCMSA |
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±1 |
± 1 |
LSB |
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Minimum Reference |
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2.3 |
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1.00 |
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2.3 |
1.2 |
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kΩ |
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Resistance |
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Maximum Reference |
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2.3 |
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6 |
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2.3 |
5.3 |
6 |
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kΩ |
Resistance |
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Maximum VREF(+) |
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VCC |
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VCC |
VCC |
V |
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Input Voltage |
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Minimum VREF(−) |
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GND |
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GND |
GND |
V |
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Input Voltage |
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Minimum VREF(+) |
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VREF(−) |
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VREF(−) |
VREF(−) |
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Input Voltage |
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Maximum VREF(−) |
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VREF(+) |
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VREF(+) |
VREF(+) |
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Input Voltage |
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Maximum VIN Input |
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VCC+0.1 |
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VCC+0.1 |
VCC+0.1 |
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Voltage |
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Minimum VIN Input |
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GND−0.1 |
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GND−0.1 |
GND−0.1 |
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Voltage |
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Maximum Analog |
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=VCC |
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CS |
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Input Leakage |
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VIN=VCC |
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3 |
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0.3 |
3 |
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µA |
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Current |
VIN=GND |
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−3 |
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−0.3 |
−3 |
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µA |
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Power Supply |
VCC |
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5V |
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5% |
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1/16 |
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± 1 |
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4 |
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± |
1/16 |
±1 4 |
± 1 |
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4 |
LSB |
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Sensitivity |
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3 |
www.national.com |
DC Electrical Characteristics
The following specifications apply for VCC=5V, unless otherwise specified. Boldface limits apply from TMIN to TMAX; all other limits TA=TJ=25ÊC.
Parameter |
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Conditions |
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ADC0820BCN, ADC0820CCN |
Limit |
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ADC0820CCJ |
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ADC0820BCV, ADC0820BCWM |
Units |
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ADC0820CCWM, ADC0820CIWM |
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Typ |
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Tested |
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Design |
Typ |
Tested |
Design |
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(Note 6) |
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Limit |
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Limit |
(Note 6) |
Limit |
Limit |
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(Note 7) |
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(Note 8) |
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(Note 7) |
(Note 8) |
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VIN(1), Logical ª1º |
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VCC=5.25V |
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CS |
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WR |
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RD |
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2.0 |
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2.0 |
2.0 |
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Input Voltage |
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Mode |
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3.5 |
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3.5 |
3.5 |
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VIN(0), Logical ª0º |
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VCC=4.75V |
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0.8 |
0.8 |
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CS |
WR |
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Input Voltage |
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Mode |
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1.5 |
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1.5 |
1.5 |
V |
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IIN(1), Logical ª1º |
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VIN(1)=5V; |
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0.005 |
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1 |
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0.005 |
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µA |
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Input Current |
VIN(1)=5V; |
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0.1 |
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0.3 |
3 |
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VIN(1)=5V; Mode |
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IIN(0), Logical ª0º |
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VIN(0)=0V; |
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−1 |
µA |
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CS |
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WR |
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Input Current |
Mode |
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VOUT(1), Logical ª1º |
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VCC=4.75V, IOUT=−360 µA; |
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2.4 |
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2.8 |
2.4 |
V |
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Output Voltage |
DB0±DB7, |
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OFL |
INT |
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VCC=4.75V, IOUT=−10 µA; |
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4.5 |
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4.6 |
4.5 |
V |
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DB0±DB7, |
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OFL |
INT |
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VOUT(0), Logical ª0º |
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VCC=4.75V, IOUT=1.6 mA; |
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0.4 |
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0.34 |
0.4 |
V |
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Output Voltage |
DB0±DB7, |
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, RDY |
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OFL |
INT |
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IOUT, TRI-STATE |
VOUT=5V; DB0±DB7, RDY |
0.1 |
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3 |
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0.1 |
0.3 |
3 |
µA |
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Output Current |
VOUT=0V; DB0±DB7, RDY |
−0.1 |
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−3 |
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−0.1 |
−0.3 |
−3 |
µA |
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ISOURCE, Output |
VOUT=0V; DB0±DB7, |
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−12 |
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−6 |
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−12 |
−7.2 |
−6 |
mA |
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OFL |
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Source Current |
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−9 |
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−4.0 |
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−9 |
−5.3 |
−4.0 |
mA |
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INT |
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ISINK, Output Sink |
VOUT=5V; DB0±DB7, |
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14 |
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7 |
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14 |
8.4 |
7 |
mA |
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OFL |
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Current |
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, RDY |
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INT |
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ICC, Supply Current |
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= |
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=0 |
7.5 |
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15 |
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7.5 |
13 |
15 |
mA |
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CS |
WR |
RD |
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AC Electrical Characteristics
The following specifications apply for VCC=5V, tr=tf=20 ns, VREF(+)=5V, VREF(−) =0V and TA=25ÊC unless otherwise specified.
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Typ |
Tested |
Design |
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Parameter |
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Conditions |
(Note 6) |
Limit |
Limit |
Units |
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(Note 7) |
(Note 8) |
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tCRD, Conversion Time for RD |
Pin 7 = 0, Figure 2 |
1.6 |
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2.5 |
µs |
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Mode |
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tACC0, Access Time (Delay from |
Pin 7 = 0, Figure 2 |
tCRD+20 |
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tCRD+50 |
ns |
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Falling Edge of |
RD |
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to Output |
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Valid) |
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tCWR-RD, Conversion Time for |
Pin 7 = VCC; tWR = 600 ns, |
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1.52 |
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WR-RD Mode |
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tRD=600 ns; Figures 3, 4 |
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tWR, Write Time |
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Min |
Pin 7 = VCC; Figures 3, 4 |
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600 |
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Max |
(Note 4) See Graph |
50 |
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µs |
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tRD, Read Time |
Min |
Pin 7 = VCC; Figures 3, 4 |
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600 |
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(Note 4) See Graph |
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tACC1, Access Time (Delay from |
Pin 7 = VCC, tRD<tI; Figure 3 |
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CL=15 pF |
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Falling Edge of |
RD |
to Output |
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190 |
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280 |
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Valid) |
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CL=100 pF |
210 |
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320 |
ns |
www.national.com |
4 |
AC Electrical Characteristics (Continued)
The following specifications apply for VCC=5V, tr=tf=20 ns, VREF(+)=5V, VREF(−) =0V and TA=25ÊC unless otherwise specified.
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Typ |
Tested |
Design |
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Parameter |
Conditions |
(Note 6) |
Limit |
Limit |
Units |
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(Note 7) |
(Note 8) |
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tACC2, Access Time (Delay from |
Pin 7 = VCC, tRD>tI; Figure 4 |
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Falling Edge of |
RD |
to Output |
CL=15 pF |
70 |
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120 |
ns |
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Valid) |
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CL=100 pF |
90 |
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150 |
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tACC3, Access Time (Delay from |
RPULLUP = 1k and CL = 15 pF |
30 |
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Rising Edge of RDY to Output |
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Valid) |
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tI, Internal Comparison Time |
Pin 7=VCC; Figures 4, 5 |
800 |
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1300 |
ns |
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CL=50 pF |
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t1H, t0H, TRI-STATE Control |
RL=1k, CL=10 pF |
100 |
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200 |
ns |
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(Delay from Rising Edge of |
RD |
to |
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Hi-Z State) |
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Pin 7 = VCC, CL= 50 pF |
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INTL, Delay from Rising Edge of |
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tRD>tI; Figure 4 |
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tI |
ns |
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WR |
to Falling Edge of |
INT |
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tRD<tI; Figure 3 |
tRD+200 |
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tRD+290 |
ns |
t |
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Figures 2, 3, 4 |
125 |
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225 |
ns |
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INTH, Delay from Rising Edge of |
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CL=50 pFc |
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RD |
to Rising Edge of |
INT |
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t |
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Figure 5, CL=50 pF |
175 |
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270 |
ns |
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INTHWR, Delay from Rising Edge of |
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WR |
to Rising Edge of |
INT |
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Figure 2, CL=50 pF, Pin 7 =0 |
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tRDY, Delay from |
CS |
to RDY |
50 |
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100 |
ns |
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tID, Delay from |
INT |
to Output Valid |
Figure 5 |
20 |
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50 |
ns |
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Pin 7=VCC, tRD<tI |
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tRI, Delay from |
RD |
to |
INT |
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200 |
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290 |
ns |
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Figure 3 |
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tP, Delay from End of Conversion |
Figures 2, 3, 4, 5 |
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500 |
ns |
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to Next Conversion |
(Note 4) See Graph |
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Slew Rate, Tracking |
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0.1 |
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V/µs |
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CVIN, Analog Input Capacitance |
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45 |
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pF |
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COUT, Logic Output Capacitance |
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5 |
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pF |
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CIN, Logic Input Capacitance |
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5 |
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pF |
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions.
Note 2: All voltages are measured with respect to the GND pin, unless otherwise specified.
Note 3: Total unadjusted error includes offset, full-scale, and linearity errors.
Note 4: Accuracy may degrade if tWR or tRD is shorter than the minimum value specified. See Accuracy vs tWR and Accuracy vs tRD graphs.
Note 5: When the input voltage (VIN) at any pin exceeds the power supply rails (VIN < V− or VIN > V+) the absolute value of current at that pin should be limited to 1 mA or less. The 4 mA package input current limits the number of pins that can exceed the power supply boundaries with a 1 mA current limit to four.
Note 6: Typicals are at 25ÊC and represent most likely parametric norm.
Note 7: Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level).
Note 8: Design limits are guaranteed but not 100% tested. These limits are not used to calculate outgoing quality levels.
Note 9: Human body model, 100 pF discharaged through a 1.5 kΩ resistor.
5 |
www.national.com |
TRI-STATE Test Circuits and Waveforms
t1H
DS005501-4
DS005501-3
tr=20 ns
t0H
DS005501-6
DS005501-5 tr=20 ns
Timing Diagrams
DS005501-7
Note: On power-up the state of INT can be high or low.
FIGURE 2. RD Mode (Pin 7 is Low)
www.national.com |
6 |
Timing Diagrams (Continued)
DS005501-8
FIGURE 3. WR-RD Mode (Pin 7 is High and tRD<tI)
DS005501-9
FIGURE 4. WR-RD Mode (Pin 7 is High and tRD>tI)
DS005501-10
FIGURE 5. WR-RD Mode (Pin 7 is High)
Stand-Alone Operation
7 |
www.national.com |