August 1998
54AC373 · 54ACT373
Octal Transparent Latch with TRI-STATE® Outputs
General Description
The 'AC/'ACT373 consists of eight latches with TRI-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus output is in the high impedance state.
Features
nICC and IOZ reduced by 50%
nEight latches in a single package
nTRI-STATE outputs for bus interfacing
nOutputs source/sink 24 mA
n'ACT373 has TTL-compatible inputs
nStandard Microcircuit Drawing (SMD)
Ð'AC373: 5962-87555
Ð'ACT373: 5962-87556
Logic Symbols
IEEE/IEC
DS100329-1
DS100329-2
|
|
Pin Names |
Description |
|
|
|
|
|
D0±D7 |
Data Inputs |
|
|
LE |
Latch Enable Input |
|
|
|
Output Enable Input |
|
|
OE |
|
|
|
O0±O7 |
TRI-STATE Latch Outputs |
|
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
FACT® is a registered trademark of Fairchild Semiconductor Corporation.
Outputs STATE-TRI with Latch Transparent Octal 54ACT373 · 54AC373
© 1998 National Semiconductor Corporation |
DS100329 |
www.national.com |
Connection Diagrams
Pin Assignment for LCC
Pin Assignment for DIP and Flatpak
DS100329-3
Functional Description
The 'AC/'ACT373 contains eight D-type latches with TRI-STATE standard outputs. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The TRI-STATE standard outputs are controlled by the Output Enable (OE) input. When OE is LOW, the standard outputs are in the 2-state mode. When OE is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches.
DS100329-4
Truth Table
|
Inputs |
|
Outputs |
||
LE |
|
OE |
|
Dn |
On |
X |
|
H |
X |
Z |
|
H |
|
L |
L |
L |
|
H |
|
L |
H |
H |
|
L |
|
L |
X |
O0 |
|
H = HIGH Voltage Level
L = LOW Voltage Level Z = High Impedance
X = Immaterial
O0 = Previous O0 before HIGH to Low transition of Latch Enable
www.national.com |
2 |
Logic Diagram
DS100329-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3 |
www.national.com |
Loading...