NSC ADC0819CIN, ADC0819CCVX, ADC0819CCV, ADC0819BCVX, ADC0819BCN Datasheet

December 1994

ADC0819 8-Bit Serial I/O A/D Converter with 19-Channel Multiplexer

General Description

The ADC0819 is an 8-Bit successive approximation A/D converter with simultaneous serial I/O. The serial input controls an analog multiplexer which selects from 19 input channels or an internal half scale test voltage.

An input sample-and-hold is implemented by a capacitive reference ladder and sampled data comparator. This allows the input signal to vary during the conversion cycle.

Separate serial I/O and conversion clock inputs are provided to facilitate the interface to various microprocessors.

Features

YSeparate asynchronous converter clock and serial data I/O clock.

Y19-Channel multiplexer with 5-Bit serial address logic.

YBuilt-in sample and hold function.

YRatiometric or absolute voltage referencing.

YNo zero or full-scale adjust required.

YInternally addressable test voltage.

Y0V to 5V input range with single 5V power supply.

YTTL/MOS input/output compatible.

Y28-pin molded chip carrier or 28-pin molded DIP

Key Specifications

Y Resolution		8-Bits
Y Total unadjusted error		g (/2LSB and g 1LSB
Y Single supply		5VDC
Y	Low Power	15 mW
Y	Conversion Time	16 ms

Connection Diagrams Functional Diagram

Molded Chip Carrier (PCC) Package

TL/H/9287 ± 1

Top View

Order Number ADC0819BCV, CCV

See NS Package Number V28A

Dual-In-Line Package

TL/H/9287 ± 2

TL/H/9287 ± 20

Top View

Order Number ADC0819BCN, CIN

See NS Package Number N28B

Multiplexer Channel-19 with Converter A/D I/O Serial Bit-8 ADC0819

C1995 National Semiconductor Corporation

TL/H/9287

RRD-B30M115/Printed in U. S. A.

Absolute Maximum Ratings (Notes 1 & 2)

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.

Supply Voltage (VCC)	6.5V
Voltage
Inputs and Outputs	b0.3V to VCC a0.3V
Input Current Per Pin (Note 3)	g5mA
Total Package Input Current (Note 3)	g20mA
Storage Temperature	b65§C to a150§C
Package Dissipation at TAe25§C	875 mW

Lead Temperature (Soldering, 10 sec.)	260§C
Dual-In-Line Package (Plastic)
Surface Mount Package	215§C
Vapor Phase (60 sec.)
Infrared (15 sec.)	220§C
ESD Susceptibility (Note 11)	2000V

Operating Ratings (Notes 1 & 2)

Supply Voltage (VCC)	4.5 VDC to 6.0 VDC
Temperature Range	TMIN s TA s TMAX
ADC0819BCV, ADC0819CCV	b40§C s TA s a85§C
ADC0819BCN	0§C s TA s a70§C
ADC0819CIN	b40§C s TA s a85§C

Electrical Characteristics

The following specifications apply for VCC e 5V, VREF e 5V, w2 CLK e 2.097 MHz unless otherwise specified. Boldface limits apply from TMIN to TMAX; all other limits TA e TJ e 25§C.

			Typical	Tested	Design
Parameter		Conditions		Limit	Limit	Units
			(Note 6)
				(Note 7)	(Note 8)
CONVERTER AND MULTIPLEXER CHARACTERISTICS
Maximum Total		VREFe5.00 VDC
Unadjusted Error		(Note 4)
ADC0819BCV, BCN				g(/2	g(/2	LSB
ADC0819CCV, CIN				g1	g1	LSB
Minimum Reference			8		5	kX
Input Resistance
Maximum Reference			8	11	11	kX
Input Resistance
Maximum Analog Input Range		(Note 5)		VCCa0.05	VCCa0.05	V
Minimum Analog Input Range				GNDb0.05	GNDb0.05	V
On Channel Leakage Current		(Note 9)
		On Channele5V		400	1000	nA
		Off Channele0V
		On Channele0V		b400	b1000	nA
		Off Channele5V
		(Note 9)
Off Channel Leakage Current		(Note 9)
		On Channele5V		b400	b1000	nA
		Off Channele0V
		On Channele0V		400	1000	nA
		Off Channele5V
		(Note 9)
Minimum VTEST		VREFeVCC,			125	(Note 10)
Internal Test Voltage		CH 19 Selected		125		Counts
Maximum VTEST		VREFeVCC,			130	(Note 10)
Internal Test Voltage		CH 19 Selected		130		Counts
DIGITAL AND DC CHARACTERISTICS
VIN(1), Logical ``1'' Input		VCCe5.25V		2.0	2.0	V
Voltage (Min)
VIN(0), Logical ``0'' Input		VCCe4.75V		0.8	0.8	V
Voltage (Max)
IIN(1), Logical ``1'' Input		VINe5.0V	0.005	2.5	2.5	mA
Current (Max)
IIN(0), Logical ``0'' Input		VINe0V	b0.005	b2.5	b2.5	mA
Current (Max)

2

Electrical Characteristics (Continued)

The following specifications apply for VCC e 5V, VREF e 5V, w2 CLK e 2.097 MHz unless otherwise specified. Boldface limits apply from TMIN to TMAX; all other limits TA e TJ e 25§C.

Typical

Tested

Design

Parameter

Conditions

Limit

Limit

Units

(Note 6)

(Note 7)

(Note 8)

DIGITAL AND DC CHARACTERISTICS (Continued)

VOUT(1), Logical ``1''

VCCe4.75V

Output Voltage (Min)

IOUTeb360 mA

2.4

2.4

V

IOUTeb10 mA

4.5

4.5

V

VOUT(0), Logical ``0''

VCCe5.25V

0.4

0.4

V

Output Voltage (Max)

IOUTe1.6 mA

IOUT, TRI-STATE Output

VOUTe0V

b0.01

b3

b3

mA

Current (Max)

VOUTe5V

0.01

3

3

mA

ISOURCE, Output Source

VOUTe0V

b14

b6.5

b6.5

mA

Current (Min)

ISINK, Output Sink Current (Min)

VOUTeVCC

16

8.0

8.0

mA

e1, VREF Open

2.5

ICC, Supply Current (Max)

CS

1

2.5

mA

IREF (Max)

VREFe5V

0.7

1

1

mA

AC CHARACTERISTICS

Tested

Design

Parameter

Conditions

Typical

Limit

Limit

Units

(Note 6)

(Note 7)

(Note 8)

w2 CLK, w2 Clock Frequency

MIN

0.70

1.0

MHz

MAX

4.0

2.0

2.1

SCLK, Serial Data Clock

MIN

5.0

KHz

Frequency

MAX

1000

525

525

TC, Conversion Process Time

MIN

Not Including MUX

26

26

w2 cycles

Addressing and

MAX

Analog Input

32

32

Sampling Times

tACC, Access Time Delay From

MIN

w2 cycles

CS

1

Falling Edge to DO Data Valid

MAX

3

tSET-UP, Minimum Set-up Time of

Falling

1

CS

sec

Edge to SCLK Rising Edge

4/w2CLKa

2 SCLK

tHCS

,

Hold Time After the Falling

CS

0

ns

Edge of SCLK

t

CS

, Total

CS

Low Time

MIN

tset-upa8/SCLK

sec

MAX

t

(min)a26/w2CLK

sec

CS

tHDI, Minimum DI Hold Time from

0

0

ns

SCLK Rising Edge

tHDO, Minimum DO Hold Time from SCLK

RLe30k,

10

ns

Falling Edge

CLe100 pF

tSDI, Minimum DI Set-up Time to SCLK

200

400

ns

Rising Edge

tDDO, Maximum Delay From SCLK

RLe30k,

180

200

250

ns

Falling Edge to DO Data Valid

CLe100 pF

tTRI, Maximum DO Hold Time,

RLe3k,

90

150

150

ns

(CS Rising edge to DO TRI-STATE)

CLe100 pF

3

Electrical Characteristics

The following specifications apply for VCC e 5V, tretfe20 ns, VREF e 5V, unless otherwise specified. Boldface limits apply from TMIN to TMAX; all other limits TAeTJe25§C.

					Typical	Tested	Design
Parameter				Conditions		Limit	Limit	Units
					(Note 6)
						(Note 7)	(Note 8)
AC CHARACTERISTICS (Continued)
tCA, Analog		After Address Is Latched					3/SCLKa1 ms	sec
Sampling Time		CSeLow
tRDO, Maximum DO		RLe30 kX,		``TRI-STATE'' to ``HIGH'' State	75	150	150	ns
Rise Time		CLe100 pf		``LOW'' to ``HIGH'' State	150	300	300
tFDO, Maximum DO		RLe30 kX,		``TRI-STATE'' to ``LOW'' State	75	150	150	ns
Fall Time		CLe100 pf		``HIGH'' to ``LOW'' State	150	300	300
CIN, Maximum Input		Analog Inputs, ANO ± AN10 and VREF			11		55	pF
Capacitance		All Others			5		15

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions.

Note 2: All voltages are measured with respect to ground.

Note 3: Under over voltage conditions (VINk0V and VINlVCC) the maximum input current at any one pin is g5 mA. If the voltage at more than one pin exceeds VCC a .3V the total package current must be limited to 20 mA. For example the maximum number of pins that can be over driven at the maximum current level of g5 mA is four.

Note 4: Total unadjusted error includes offset, full-scale, linearity, multiplexer, and hold step errors.

Note 5: Two on-chip diodes are tied to each analog input, which will forward-conduct for analog input voltages one diode drop below ground or one diode drop greater than VCC supply. Be careful during testing at low VCC levels (4.5V), as high level analog inputs (5V) can cause this input diode to conduct, especially at elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows 50 mV forward bias of either diode. This means that as long as the analog VIN does not exceed the supply voltage by more than 50 mV, the output code will be correct. To achieve an absolute 0 VDC to 5 VDC input voltage range will therefore require a minimum supply voltage of 4.950 VDC over temperature variations, initial tolerance and loading.

Note 6: Typicals are at 25§C and represent most likely parametric norm.

Note 7: Tested Limits are guaranteed to National's AOQL (Average Outgoing Quality Level).

Note 8: Design Limits are guaranteed, but not 100% production tested. These limits are not used to calculate outgoing quality levels.

Note 9: Channel leakage current is measured after the channel selection.

Note 10: 1 count e VREF/256.

Note 11: Human body model; 100 pF discharged through a 1.5 kX resistor.

Test Circuits

Leakage Current	D0 Except ``TRI-STATE''

TL/H/9287 ± 4

TL/H/9287 ± 3

tTRI ``TRI-STATE''	Timing Diagrams
	D0 ``TRI-STATE'' Rise & Fall Times

TL/H/9287 ± 6

TL/H/9287 ± 5

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