NSC 5962R9160301VFA, 5962R9160301VEA, 5962R9160301V2A, 5962R9160301MFA, 5962R9160301MEA Datasheet

July 1998

54AC169 · 54ACT169

4-Stage Synchronous Bidirectional Counter

General Description

The 'AC/'ACT169 is fully synchronous 4-stage up/down counter. The 'AC/'ACT169 is a modulo-16 binary counter. It features a preset capability for programmable operation, carry lookahead for easy cascading and a U/D input to control the direction of counting. All state changes, whether in counting or parallel loading, are initiated by the LOW-to-HIGH transition of the Clock.

nSynchronous counting and loading

nBuilt-In lookahead carry capability

nPresettable for programmable operation

nOutputs source/sink 24 mA

n'ACT has TTL-compatible inputs

nStandard Microcircuit Drawing (SMD) 5962-91603

Features

n ICC reduced by 50%

Logic Symbols
				Pin						Description
			Names
										Count Enable Parallel Input
			CEP
										Count Enable Trickle Input
		CET
		CP								Clock Pulse Input
		P0±P3								Parallel Data Inputs
										Parallel Enable Input
		PE
										Up-Down Count Control Input
		U/D
DS100276-1		Q0±Q3								Flip-Flop Outputs
										Terminal Count Output
		TC

IEEE/IEC

DS100276-2

FACT™ is a trademark of Fairchild Semiconductor Corporation.

Counter Bidirectional Synchronous Stage-4 54ACT169 · 54AC169

© 1998 National Semiconductor Corporation

DS100276

www.national.com

Connection Diagrams

Pin Assignment	Pin Assignment
for DIP and Flatpak	for LCC

DS100276-3

DS100276-4

Logic Diagram

DS100276-5

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

Functional Description

The 'AC/'ACT169 uses edge-triggered J-K-type flip-flops and have no constraints on changing the control or data input signals in either state of the Clock. The only requirement is that the various inputs attain the desired state at least a setup time before the rising edge of the clock and remain valid for the recommended hold time thereafter. The parallel load operation takes precedence over the other operations, as indicated in the Mode Select Table. When PE is LOW, the

data on the P0±P3 inputs enters the flip-flops on the next ris- ing edge of the Clock. In order for counting to occur, both CEP and CET must be LOW and PE must be HIGH; the U/D input then determines the direction of counting. The Terminal Count (TC) output is normally HIGH and goes LOW, provided that CET is LOW, when a counter reaches zero in the Count Down mode or reaches 15 in the Count Up mode. The TC output state is not a function of the Count Enable Parallel (CEP) input level. If an illegal state occurs, the 'AC169 will return to the legitimate sequence within two counts. Since

www.national.com

2

Functional Description (Continued)

State Diagrams

the TC signal is derived by decoding the flip-flop states, there exists the possibility of decoding spikes on TC. For this reason the use of TC as a clock signal is not recommended (see logic equations below).

1.Count Enable = CEP · CET · PE

2.Up: TC = Q0· Q1· Q 2Q3· (Up)· CET

3.Down: TC = Q0· Q1· Q2· Q3 · (Down)· CET

Mode Select Table

											DS100276-6
	PE		CEP		CET		U/D			Action on Rising
										Clock Edge
	L		X		X		X			Load (Pn to Qn)
	H		L		L		H			Count Up (Increment)
	H		L		L		L			Count Down (Decrement)
	H		H		X		X			No Change (Hold)
	H		X		H		X			No Change (Hold)

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial

3	www.national.com