August 1998
54AC374 · 54ACT374
Octal D Flip-Flop with TRI-STATE® Outputs
General Description
The 'AC/'ACT374 is a high-speed, low-power octal D-type flip-flop featuring separate D-type inputs for each flip-flop and TRI-STATE outputs for bus-oriented applications. A buffered Clock (CP) and Output Enable (OE) are common to all flip-flops.
Features
nICC and IOZ reduced by 50%
nBuffered positive edge-triggered clock
nTRI-STATE outputs for bus-oriented applications
nOutputs source/sink 24 mA
nSee '273 for reset version
nSee '377 for clock enable version
nSee '373 for transparent latch version
nSee '574 for broadside pinout version
nSee '564 for broadside pinout version with inverted outputs
n'ACT374 has TTL-compatible inputs
nStandard Military Drawing (SMD)
Ð'AC374: 5962-87694
Ð'ACT374: 5962-87631
Logic Symbols
IEEE/IEC
DS100289-1
DS100289-2
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Pin |
Description |
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Names |
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D0±D7 |
Data Inputs |
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CP |
Clock Pulse Input |
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TRI-STATE Output Enable Input |
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OE |
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O0±O7 |
TRI-STATE Outputs |
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TRI-STATE® is a registered trademark of National Semiconductor Corporation.
FACT® is a registered trademark of Fairchild Semiconductor Corporation.
Outputs STATE-TRI with Flop-Flip D Octal 54ACT374 · 54AC374
© 1998 National Semiconductor Corporation |
DS100289 |
www.national.com |
Connection Diagrams
Pin Assignment for DIP |
Pin Assignment for LCC |
and Flatpak |
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DS100289-3
Functional Description
The 'AC/'ACT374 consists of eight edge-triggered flip-flops with individual D-type inputs and TRI-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transition. With the Output Enable (OE) LOW, the contents of the eight flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops.
Logic Diagram
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DS100289-4 |
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Truth Table |
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Inputs |
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Outputs |
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Dn |
CP |
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OE |
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On |
H |
N |
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L |
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H |
L |
N |
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L |
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L |
X |
X |
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H |
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Z |
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H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
N = LOW-to-HIGH Transition
DS100289-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2 |
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.
Supply Voltage (VCC) |
−0.5V to +7.0V |
DC Input Diode Current (IIK) |
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VI = −0.5V |
−20 mA |
VI = VCC + 0.5V |
+20 mA |
DC Input Voltage (VI) |
−0.5V to V CC + 0.5V |
DC Output Diode Current (IOK) |
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VO = −0.5V |
−20 mA |
VO = VCC + 0.5V |
+20 mA |
DC Output Voltage (VO) |
−0.5V to V CC + 0.5V |
DC Output Source |
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or Sink Current (IO) |
±50 mA |
DC VCC or Ground Current |
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per Output Pin (ICC or IGND) |
±50 mA |
Storage Temperature (TSTG) |
−65ÊC to +150ÊC |
Junction Temperature (TJ) |
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CDIP |
175ÊC |
Recommended Operating
Conditions
Supply Voltage (VCC) |
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'AC |
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2.0V to 6.0V |
'ACT |
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4.5V to 5.5V |
Input Voltage (VI) |
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0V to VCC |
Output Voltage (VO) |
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0V to VCC |
Operating Temperature (TA) |
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54AC/ACT |
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−55ÊC to +125ÊC |
Minimum Input Edge Rate ( |
V/ |
t) |
'AC Devices |
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VIN from 30% to 70% of VCC |
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VCC @ 3.3V, 4.5V, 5.5V |
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125 mV/ns |
Minimum Input Edge Rate ( |
V/ |
t) |
'ACT Devices |
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VIN from 0.8V to 2.0V |
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VCC @ 4.5V, 5.5V |
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125 mV/ns |
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of FACT® circuits outside databook specifications.
DC Characteristics for 'AC Family Devices
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54AC |
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Symbol |
Parameter |
VCC |
TA = −55ÊC to +125ÊC |
Units |
Conditions |
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(V) |
Guaranteed Limits |
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VIH |
Minimum High |
3.0 |
2.1 |
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VOUT = 0.1V |
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Level Input |
4.5 |
3.15 |
V |
or VCC − 0.1V |
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Voltage |
5.5 |
3.85 |
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VIL |
Maximum Low |
3.0 |
0.9 |
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VOUT = 0.1V |
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Level Input |
4.5 |
1.35 |
V |
or VCC − 0.1V |
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Voltage |
5.5 |
1.65 |
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VOH |
Minimum High |
3.0 |
2.9 |
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IOUT = −50 µA |
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Level Output |
4.5 |
4.4 |
V |
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Voltage |
5.5 |
5.4 |
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(Note 2) |
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VIN = VIL or VIH |
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3.0 |
2.4 |
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−12 mA |
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4.5 |
3.7 |
V |
IOH |
−24 mA |
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5.5 |
4.7 |
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−24 mA |
VOL |
Maximum Low |
3.0 |
0.1 |
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IOUT = 50 µA |
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Level Output |
4.5 |
0.1 |
V |
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Voltage |
5.5 |
0.1 |
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(Note 2) |
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VIN = VIL or VIH |
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3.0 |
0.50 |
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12 mA |
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4.5 |
0.50 |
V |
IOL |
24 mA |
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5.5 |
0.50 |
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24 mA |
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IIN |
Maximum Input |
5.5 |
±1.0 |
µA |
VI = VCC, GND |
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Leakage Current |
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IOZ |
Maximum |
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VI (OE) = VIL, VIH |
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TRI-STATE |
5.5 |
±5.0 |
µA |
VI = VCC, GND |
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Current |
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VO = VCC, GND |
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3 |
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