NSC ADC0858CMJ-QML, ADC0858CIVX, ADC0858CIN, ADC0858BIVX, ADC0858BIV Datasheet

MICROWIRETM

January 1995

ADC0851 and ADC0858 8-Bit Analog Data

Acquisition and Monitoring Systems

General Description

The ADC0851 and ADC0858 are 2 and 8 input analog data acquisition systems. They can function as conventional multiple input A/D converters, automatic scanning A/D converters or programmable analog ``watchdog'' systems. In ``watchdog'' mode they monitor analog inputs and determine whether these inputs are inside or outside user programmed window limits. This monitoring process takes place independent of the host processor. When any input falls outside of its programmed window limits, an interrupt is automatically generated which flags the processor; the chip can then be interrogated as to exactly which channels crossed which limits.

The advantage of this approach is that its frees the processor from having to frequently monitor analog variables. It can consequently save having to insert many A/D subroutine calls throughout real time application code. In control systems where many variables are continually being monitored this can significantly free up the processor, especially if the variables are DC or slow varying signals.

The Auto A/D conversion feature allows the device to scan through selected input channels, performing an A/D conversion on each channel without the need to select a new channel after each conversion.

Key Specifications

Y Resolution		8 Bits
Y Total error		g(/2 LSB or g 1 LSB
Y Low power		50 mW
Y	Conversion time	18 ms/Channel
Y	Limit comparison time	2 ms/Limit

Features

YWatchdog operation signals processor when any channel is outside user programmed window limits

YFrees microprocessor from continually monitoring analog signals and simplifies applications software

Y2 (ADC0851) or 8 (ADC0858) analog input channels

YSingle ended or differential input pairs

YCOM input for DC offsetting of input voltage

Y4 (ADC0851) and 16 (ADC0858), 8-bit programmable limits

YNSC MICROWIRETM interface

YPower fail detection

YAuto A/D conversion feature

YSingle 5V supply

YWindow limits are user programmable via serial interface

Applications

YInstrumentation monitoring and process control

YDigitizing automotive sensor signals

YEmbedded diagnostics

Simplified Block Diagram

TL/H/11021 ± 22

FIGURE 1

TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. is a trademark of National Semiconductor Corporation.

Systems Monitoring and Acquisition Data Analog Bit-8 ADC0858 and ADC0851

C1995 National Semiconductor Corporation

TL/H/11021

RRD-B30M75/Printed in U. S. A.

Connection Diagrams

ADC0851	ADC0858
2-Channel MUX	8-Channel MUX
Dual-In-Line Package	Dual-In-Line Package

TL/H/11021 ± 1

Top View

ADC0851 PLCC Package

TL/H/11021 ± 3

Top View
Ordering Information
Industrial		Package
(b40§C s TA s a85§C)
ADC0851BIN,		N16E, 16-Pin
ADC0851CIN		Plastic DIP
ADC0858BIN,		N20A, 20-Pin
ADC0858CIN		Plastic DIP
ADC0851BIV,		V20A, 20-Lead
ADC0851CIV		PLCC
ADC0858BIV,		V20A, 20-Lead
ADC0858CIV		PLCC

TL/H/11021 ± 2

Top View

ADC0858 PLCC Package

		TL/H/11021 ± 4
	Top View
	Military	Package
	(b55§C s TA s a125§C)
	ADC0851CMJ/883	J16A, 16-Pin
		Ceramic DIP
	ADC0858CMJ/883	J20A, 20-Pin
		Ceramic DIP

2

Absolute Maximum Ratings (Notes 1 & 2)

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.

Supply Voltage, VCC	6.5V
Voltage at Logic and Analog
Inputs (Note 3)	b0.3V to VCC a 0.3V
Input Current per Pin	g5 mA
Input Current per Package	g20 mA
Storage Temperature	b65§C to a150§C
Package Dissipation	500 mW
at TA e a25§C (Board Mount)	800 mW
Lead Temperature (Soldering, 10 Sec.)
Dual-In-Line (Plastic)	a260§C
Dual-In-Line (Ceramic)	a300§C
ESD Susceptibility (Note 4)	2000V

Operating Ratings (Notes 1 & 2)

Supply Voltage, VCC	4.5V to 5.5V
Temperature Range	TMIN s TA s TMAX
ADC0858CMJ/883	b55§C s TA s a125§C
ADC0851CMJ/883	b55§C s TA s a125§C
ADC0858BIN, ADC0858CIN	b40§C s TA s a85§C
ADC0851BIN, ADC0851CIN	b40§C s TA s a85§C
ADC0858BIV, ADC0858CIV	b40§C s TA s a85§C
ADC0851BIV, ADC0851CIV	b40§C s TA s a85§C

DC Electrical Characteristics

The following specifications apply for VCC e a5 VDC, VREF e a4.5 VDC, AGND e DGND e 0V and fOSC e 1 MHz (Rext e 3.16 kX, Cext e 170 pF) unless otherwise specified. Boldface limits apply for TA e TJ e TMIN to TMAX; all other limits apply

at TA e TJ e a25§C.

	Parameter	Conditions	Typical	Limit	Units
			(Note 5)	(Note 6)	(Limits)
	CONVERTER AND MULTIPLEXER CHARACTERISTICS
	Total Unadjusted Error (Note 7)
	ADC0851/8/BIN, ADC0851/8/BIV			g(/2	LSB (Max)
	ADC0851/8/CIN, ADC0851/8/CMJ,			g1	LSB (Max)
	ADC0851/8/CIV			g1	LSB (Max)
	Comparator Offset
	ADC0851/8/BIN, ADC0858BIV		g2.5	g10	mV (Max)
	ADC0851/8/CIN, ADC0851/8/CMJ,		g2.5	g20	mV (Max)
	ADC0858CIV		g2.5	g20	mV (Max)
	VREF Input Resistance		6	3.5	kX (Min)
				10	kX (Max)
	Common Mode Input Voltage	All MUX Inputs		GND b 0.05	V (Min)
	(Note 8)	and COM Input		VCC a 0.05	V (Max)
	DC Common Mode Error	DVCM e b0.05V to a5.05V	g1/16	g1/4	LSB (Max)
	Power Supply Sensitivity	VREF e 4.75V
		VCC e 5V g 5%	g1/16	g1/4	LSB (Max)
		VREF e 4.5V	g1/16	g1/2
		VCC e 5V g 10%
	IOFF,	On Channel e 5V	b0.01	b3	mA (Max)
	Off Channel	Off Channel e 0V
	Leakage Current	On Channel e 0V
	(Note 9)		a0.01	a3	mA (Max)
		Off Channel e 5V
	ION,	On Channel e 5V	a0.01	a3	mA (Max)
	On Channel	Off Channel e 0V
	Leakage Current	On Channel e 0V
	(Note 9)		b0.01	b3	mA (Max)
		Off Channel e 5V

3

DC Electrical Characteristics (Continued)

The following specifications apply for VCC e a5 VDC, VREF e a4.5 VDC, AGND e DGND e 0V and fOSC e 1 MHz (Rext e 3.16 kX, Cext e 170 pF) unless otherwise specified. Boldface limits apply for TA e TJ e TMIN to TMAX; all other limits apply

at TA e TJ e a25§C.

Parameter					Conditions	Typical	Limit	Units
						(Note 5)	(Note 6)	(Limits)
DIGITAL CHARACTERISTICS
Logic ``1'' Input				VCC e 5.5V			2.2	V (Min)
Voltage, VIH
Logic ``0'' Input				VCC e 4.5V			0.8	V(Max)
Voltage, VIL
Logic ``1'' Input				VIN e VCC		0.005	3	mA (Max)
Current, IIH
Logic ``0'' Input				VIN e 0V		b0.005	b3	mA (Max)
Current, IIL
Logic ``1'' Output				VCC e 4.5V
Voltage, VOH			IOUT e b360 mA				2.4	V (Min)
			IOUT e b10 mA				4.2
(Except INT)								V (Min)
Logic ``0'' Output				IOUT e 1.6 mA			0.4	V (Max)
Voltage, VOL			VCC e 4.5V
TRI-STATEÉ Output					e Logic ``1'' (5V)
				CS
Current (DO)			VOUT e 0.4V			b0.1	b3	mA (Max)
			VOUT e 5V			0.1	3	mA (Max)
ISOURCE			VOUT Short to GND			b14	b6.5	mA (Min)
(Except INT)
ISINK			VOUT Short to VCC			16	8	mA (Min)
Supply Current, ICC			fCLK e 1 MHz			7	10	mA (Max)
ADC0851 or ADC0858				fCLK e 2 MHz		7.2		mA
			(Note 10)

AC Electrical Characteristics

The following specifications apply for VCC e a5 VDC, VREF e a4.5 VDC, AGND e DGND e 0V, fCLK e 1 MHz, tr e tf e 5 ns unless otherwise specified. Boldface limits apply for TA e TJ e TMIN to TMAX; all other limits apply at TA e TJ e 25§C.

Symbol			Parameter	Conditions	Typical	Limit	Units
					(Note 5)	(Note 6)	(Limits)
fCLK	Data Clock Frequency				1	2	MHz (Max)
	Clock Duty Cycle					40	% (Min)
	(Note 11)					60	% (Max)
tSET-UP	CS Falling Edge or
	Data Input Valid to				30	70	ns (Min)
	CLK Rising Edge
tHOLD	Data Input Valid after				5	30	ns (Min)
	CLK Rising Edge
tPD1, tPD0	CLK Rising Edge to			CL e 100 pF	80	200	ns (Max)
	Output Data Valid

4

AC Electrical Characteristics (Continued)

The following specifications apply for VCC e a5 VDC, VREF e a4.5 VDC, AGND e DGND e 0V, fCLK e 1 MHz, tr e tf e 5 ns unless otherwise specified. Boldface limits apply for TA e TJ e TMIN to TMAX; all other limits apply at TA e TJ e 25§C.

Symbol

Parameter

Conditions

Typical

Limit

Units

(Note 5)

(Note 6)

(Limits)

C e 100 pF, R e 2k

t1H, t0H

Rising Edge of CS to

Data Output Hi-Z

(See TRI-STATE

90

200

ns (Max)

Test Circuits)

fOSC

Oscillator Clock Freq.

Rext e 3.16 kX

1

1.4

MHz (Max)

(Analog Timing)

Cext e 170 pF

0.6

MHz (Min)

tEOC

CS to End of

OSC Clock

Conversion Delay

Periods

1

Min

2

Max

tConv

Conversion Time

OSC Clock

Periods

17

(Min)

18

(Max)

120

t

-

CS to Interrupt Delay

60

ns (Max)

CS

INT

CIN

Capacitance of

5

pF

Logic Input

COUT

Capacitance of

5

pF

Logic Output

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.

Note 2: All voltages are measured with respect to ground (AGND e DGND e 0V).

Note 3: All of the analog and digital input pins are internally diode clamped to the supply pins. Should the applied voltage at any pin exceed the power supply voltage, the additional absolute value of current at that pin (caused by the forward biasing of the internal diodes) should be limited to 5 mA or less.

Note 4: Human body model, 100 pF discharged through a 1.5 kX resistor.

Note 5: Typical specifications are at a25§C and represent the most likely parametric norm.

Note 6: Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level).

Note 7: Total unadjusted error includes comparator offset, ADC linearity and multiplexer error, and, is expressed in LSBs.

Note 8: Two on-chip diodes are tied to each analog input. The diodes will forward conduct for analog input voltages one diode drop below ground or one diode drop above VCC. Care should be exercised when operating the device at low supply voltages (e.g., VCC e 4.5V) because high analog inputs (5V) can cause the input diodes to conduct, especially at elevated temperatures. This will cause errors for analog inputs near full scale. The specification allows 50 mV forward bias of either clamp diode. Thus as long as VIN or VREF does not exceed the supply voltage by more than 50 mV, the output code will be correct. To achieve an absolute 0 VDC to 5 VDC input voltage range will therefore require a minimum supply voltage of 4.950 VDC.

Note 9: Leakage current is measured with the oscillator clock disabled.

Note 10: Measured supply current does not include the DAC ladder current.

Note 11: A 40% to 60% clock duty cycle range ensures proper operation at all clock frequencies.

5

Typical Performance Characteristics

Offset Error vs	Linearity Error vs	Total Unadjusted Error
Reference Voltage	Reference Voltage	vs Temperature

TL/H/11021 ± 5

6

Test Circuits and Waveforms

t1H	t1H, CL e 10 pF

TL/H/11021 ± 6

TL/H/11021 ± 8

t0H	t1H, CL e 10 pF

TL/H/11021 ± 7

TL/H/11021 ± 9

Timing Diagrams

Data Input Timing

Data Output Timing

TL/H/11021 ± 11

TL/H/11021 ± 10

7

Timing Diagrams (Continued)

Watchdog Timing

TL/H/11021 ± 12

A/D Conversion Timing

TL/H/11021 ± 13

Timing Diagrams for ADC0851 and ADC0858

Read Power Flag after Power Up ADC0851/ADC0858

TL/H/11021 ± 14

8

Timing Diagrams for ADC0851 and ADC0858 (Continued)

TL/H/11021 ± 15

TL/H/11021 ± 16

Write 1 Limit to ADC0851/ADC0858

9

Write all Limits to ADC0851/ADC0858

Read 1 Limit from ADC0851/ADC0858

10

Read all Limits from ADC0851/ADC0858

TL/H/11021 ± 17

TL/H/11021 ± 18

TL/H/11021 ± 19

(Continued) ADC0858 and ADC0851 for Diagrams Timing

Timing Diagrams for ADC0851 and ADC0858 (Continued)

TL/H/11021 ± 20

TL/H/11021 ± 21

1 A/D Conversion ADC0851/ADC0858

Auto A/D Conversion ADC0851/ADC0858

11