December 1994
54F/74F74
Dual D-Type Positive Edge-Triggered Flip-Flop
General Description
The 'F74 is a dual D-type flip-flop with Direct Clear and Set inputs and complementary (Q, Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. After the Clock Pulse input threshold voltage has been passed, the Data input is locked out and information present will not be transferred to the outputs until the next rising edge of the Clock Pulse input.
Asynchronous Inputs:
LOW input to SD sets Q to HIGH level
LOW input to CD sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD
makes both Q and Q HIGH
Features
Y Guaranteed 4000V minimum ESD protection
Commercial |
Military |
Package |
Package Description |
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Number |
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74F74PC |
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N14A |
14-Lead (0.300× Wide) Molded Dual-In-Line |
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54F74DM (Note 2) |
J14A |
14-Lead Ceramic Dual-In-Line |
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74F74SC (Note 1) |
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M14A |
14-Lead (0.150× Wide) Molded Small Outline, JEDEC |
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74F74SJ (Note 1) |
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M14D |
14-Lead (0.300× Wide) Molded Small Outline, EIAJ |
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54F74FM (Note 2) |
W14B |
14-Lead Cerpack |
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54F74LM (Note 2) |
E20A |
20-Lead Ceramic Leadless Chip Carrier, Type C |
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Note 1: Devices also available in 13× reel. Use Suffix e SCX.
Note 2: Military grade device with environmental and burn-in processing. Use suffix e DMQB, FMQB and LMQB.
Logic Symbols
IEEE/IEC
TL/F/9469 ± 6
TL/F/9469 ± 3 |
TL/F/9469 ± 4 |
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
Flop-Flip Triggered-Edge Positive Type-D Dual 54F/74F74
C1995 National Semiconductor Corporation |
TL/F/9469 |
RRD-B30M75/Printed in U. S. A. |
Connection Diagrams
Pin Assignment |
Pin Assignment |
for DIP, SOIC, and Flatpak |
for LCC |
TL/F/9469 ± 1
TL/F/9469 ± 2
Unit Loading/Fan Out
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54F/74F |
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Pin Names |
Description |
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U.L. |
Input IIH/IIL |
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HIGH/LOW |
Output IOH/IOL |
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D1, D2 |
Data Inputs |
1.0/1.0 |
20 mA/b0.6 mA |
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CP1, CP2 |
Clock Pulse Inputs (Active Rising Edge) |
1.0/1.0 |
20 mA/b0.6 mA |
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20 mA/b1.8 mA |
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CD1, CD2 |
Direct Clear Inputs (Active LOW) |
1.0/3.0 |
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20 mA/b1.8 mA |
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SD1, SD2 |
Direct Set Inputs (Active LOW) |
1.0/3.0 |
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b1 mA/20 mA |
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Q1, Q1, Q2, Q2 |
Outputs |
50/33.3 |
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Truth Table
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Inputs |
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Outputs |
H (h) e HIGH Voltage Level |
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SD |
CD |
CP |
D |
Q |
Q |
L (l) e LOW Voltage Level |
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L |
H |
X |
X |
H |
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X e Immaterial |
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H |
L |
X |
X |
L |
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H |
Q0 e Previous Q |
(Q) |
before LOW-to-HIGH Clock Transition |
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L |
L |
X |
X |
H |
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H |
Lower case letters indicate the state of the referenced input or output one |
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H |
H |
L |
h |
H |
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L |
setup time prior to the LOW-to-HIGH clock transition. |
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H |
H |
L |
l |
L |
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H |
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H |
H |
L |
X |
Q0 |
Q0 |
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Logic Diagram
TL/F/9469 ± 5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
2
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature |
b65§C to a150§C |
Ambient Temperature under Bias |
b55§C to a125§C |
Junction Temperature under Bias |
b55§C to a175§C |
Plastic |
b55§C to a150§C |
VCC Pin Potential to |
b0.5V to a7.0V |
Ground Pin |
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Input Voltage (Note 2) |
b0.5V to a7.0V |
Input Current (Note 2) |
b30 mA to a5.0 mA |
Voltage Applied to Output |
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in HIGH State (with VCC e 0V) |
b0.5V to VCC |
Standard Output |
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TRI-STATEÉ Output |
b0.5V to a5.5V |
Current Applied to Output |
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in LOW State (Max) |
twice the rated IOL (mA) |
ESD Last Passing Voltage (Min) |
4000V |
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature |
b55§C to a125§C |
Military |
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Commercial |
0§C to a70§C |
Supply Voltage |
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Military |
a4.5V to a5.5V |
Commercial |
a4.5V to a5.5V |
DC Electrical Characteristics
Symbol |
Parameter |
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54F/74F |
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Units |
VCC |
Conditions |
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Min |
Typ |
Max |
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VIH |
Input HIGH Voltage |
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2.0 |
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V |
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Recognized as a HIGH Signal |
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VIL |
Input LOW Voltage |
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0.8 |
V |
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Recognized as a LOW Signal |
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VCD |
Input Clamp Diode Voltage |
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b1.2 |
V |
Min |
IIN e b18 mA |
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VOH |
Output HIGH |
54F |
10% VCC |
2.5 |
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IOH e b1 mA |
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Voltage |
74F |
10% VCC |
2.5 |
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V |
Min |
IOH e b1 mA |
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74F |
5% VCC |
2.7 |
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IOH e b1 mA |
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VOL |
Output LOW |
54F |
10% VCC |
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0.5 |
V |
Min |
IOL e 20 mA |
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Voltage |
74F |
10% VCC |
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0.5 |
IOL e 20 mA |
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IIH |
Input HIGH |
54F |
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20.0 |
mA |
Max |
VIN e 2.7V |
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Current |
74F |
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5.0 |
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IBVI |
Input HIGH Current |
54F |
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100 |
mA |
Max |
VIN e 7.0V |
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Breakdown Test |
74F |
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7.0 |
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ICEX |
Output HIGH |
54F |
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250 |
mA |
Max |
VOUT e VCC |
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Leakage Current |
74F |
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50 |
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VID |
Input Leakage |
74F |
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4.75 |
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V |
0.0 |
IID e 1.9 mA |
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Test |
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All Other Pins Grounded |
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IOD |
Output Leakage |
74F |
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3.75 |
mA |
0.0 |
VIOD e 150 mV |
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Circuit Current |
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All Other Pins Grounded |
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IIL |
Input LOW Current |
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b0.6 |
mA |
Max |
VIN e 0.5V (D, CP) |
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b1.8 |
VIN e 0.5V (CD, SD) |
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IOS |
Output Short-Circuit Current |
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b60 |
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b150 |
mA |
Max |
VOUT e 0V |
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ICC |
Power Supply Current |
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10.5 |
16.0 |
mA |
Max |
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3
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