NSC 5962R9172201VFA, 5962R9172201V2A, 5962R9172201MFA, 5962R9172201MEA, 5962R9172201M2A Datasheet

November 1998

54AC161 · 54ACT161

Synchronous Presettable Binary Counter

General Description

The 'AC/'ACT161 are high-speed synchronous modulo-16 binary counters. They are synchronously presettable for application in programmable dividers and have two types of Count Enable inputs plus a Terminal Count output for versatility in forming synchronous multistage counters. The 'AC/ 'ACT161 has an asynchronous Master Reset input that overrides all other inputs and forces the outputs LOW.

nSynchronous counting and loading

nHigh-speed synchronous expansion

nTypical count rate of 125 MHz

nOutputs source/sink 24 mA

n'ACT161 has TTL-compatible inputs

nStandard Microcircuit Drawing (SMD)

Ð'AC161: 5962-89561

Ð'ACT161: 5962-91722

Features

n ICC reduced by 50%

Logic Symbols
			Pin Names			Description
			CEP			Count Enable Parallel Input
			CET			Count Enable Trickle Input
			CP			Clock Pulse Input
						Asynchronous Master Reset Input
			MR
			P0±P3			Parallel Data Inputs
						Parallel Enable Inputs
			PE
			Q0±Q3			Flip-Flop Outputs
			TC			Terminal Count Output
IEEE/IEC	DS100274-1

DS100274-2

TRI-STATE® is a registered trademark of National Semiconductor Corporation.

FACT™ is a trademark of Fairchild Semiconductor Corporation.

Counter Binary Presettable Synchronous 54ACT161 · 54AC161

© 1998 National Semiconductor Corporation

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Connection Diagrams

Pin Assignment for DIP and Flatpak

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Pin Assignment

for LCC

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Functional Description

The 'AC/'ACT161 count in modulo-16 binary sequence. From state 15 (HHHH) they increment to state 0 (LLLL). The clock inputs of all flip-flops are driven in parallel through a clock buffer. Thus all changes of the Q outputs (except due to Master Reset of the '161) occur as a result of, and synchronous with, the LOW-to-HIGH transition of the CP input signal. The circuits have four fundamental modes of operation, in order of precedence: asynchronous reset, parallel load, count-up and hold. Five control inputs Ð Master Reset, Parallel Enable (PE), Count Enable Parallel (CEP) and Count Enable Trickle (CET) Ð determine the mode of opera- tion, as shown in the Mode Select Table. A LOW signal on MR overrides all other inputs and asynchronously forces all outputs LOW. A LOW signal on PE overrides counting and allows information on the Parallel Data (Pn) inputs to be loaded into the flip-flops on the next rising edge of CP. With PE and MR HIGH, CEP and CET permit counting when both are HIGH. Conversely, a LOW signal on either CEP or CET inhibits counting.

The 'AC/'ACT161 use D-type edge-triggered flip-flops and changing the PE, CEP and CET inputs when the CP is in either state does not cause errors, provided that the recommended setup and hold times, with respect to the rising edge of CP, are observed.

The Terminal Count (TC) output is HIGH when CET is HIGH and counter is in state 15. To implement synchronous multistage counters, the TC outputs can be used with the CEP and CET inputs in two different ways.

Figure 1 shows the connections for simple ripple carry, in which the clock period must be longer than the CP to TC delay of the first stage, plus the cumulative CET to TC delays of the intermediate stages, plus the CET to CP setup time of the last stage. This total delay plus setup time sets the upper limit on clock frequency. For faster clock rates, the carry lookahead connections shown in Figure 2 are recommended. In this scheme the ripple delay through the intermediate stages commences with the same clock that causes the first stage to tick over from max to min in the Up mode, or min to max in the Down mode, to start its final cycle. Since this final cycle requires 16 clocks to complete, there is plenty of time for the ripple to progress through the intermediate stages. The critical timing that limits the clock period is the CP to TC delay of the first stage plus the CEP to CP setup time of the last stage. The TC output is subject to decoding spikes due to internal race conditions and is therefore not recommended for use as a clock or asynchronous reset for flip-flops, registers or counters.

Logic Equations: Count Enable = CEP · CET · PE TC = Q0 · Q1 · Q2 · Q3 · CET

Mode Select Table

PE			CET	CEP	Action on the Rising
					Clock Edge (N)
	X		X	X	Reset (Clear)
	L		X	X	Load (Pn→Qn)
	H		H	H	Count (Increment)
	H		L	X	No Change (Hold)
	H		X	L	No Change (Hold)

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial

State Diagram

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State Diagram (Continued)

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FIGURE 1. Multistage Counter with Ripple Carry

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FIGURE 2. Multistage Counter with Lookahead Carry

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Diagram Block

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Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.