September 1998
54AC153 · 54ACT153 Dual 4-Input Multiplexer
General Description
The 'AC/'ACT153 is a high-speed dual 4-input multiplexer with common select inputs and individual enable inputs for each section. It can select two lines of data from four sources. The two buffered outputs present data in the true (non-inverted) form. In addition to multiplexer operation, the 'AC/'ACT153 can act as a function generator and generate any two functions of three variables.
Features
nICC reduced by 50%
nOutputs source/sink 24 mA
n'ACT153 has TTL-compatible inputs
nStandard Microcircuit Drawings (SMD)
Ð'AC153: 5962-87625
Ð'ACT153: 5962-87698
Logic Symbols
IEEE/IEC
DS100271-1
DS100271-2
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Pin |
Description |
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Names |
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I0a±I3a |
Side A Data Inputs |
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I0b±I3b |
Side B Data Inputs |
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S0, S1 |
Common Select |
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Inputs |
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a |
Side A Enable Input |
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E |
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Side B Enable Input |
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E |
b |
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Za |
Side A Output |
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Zb |
Side B Output |
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FACT® is a registered trademark of Fairchild Semiconductor Corporation.
Multiplexer Input-4 Dual 54ACT153 · 54AC153
© 1998 National Semiconductor Corporation |
DS100271 |
www.national.com |
Connection Diagrams
Pin Assignment |
Pin Assignment |
for DIP and Flatpak |
for LCC |
DS100271-3
Functional Description
The 'AC/'ACT153 is a dual 4-input multiplexer. It can select two bits of data from up to four sources under the control of the common Select inputs (S0, S1). The two 4-input multiplexer circuits have individual active-LOW Enables (Ea, Eb) which can be used to strobe the outputs indepedently. When the Enables (Ea, Eb) are HIGH, the corresponding outputs Za, Zb) are forced LOW. The 'AC/'ACT153 is the logic implementation of a 2-pole, 4-position switch, where the position of the switch is determined by the logic levels supplied to the Select inputs. The logic equations for the outputs are shown below.
Za = Ea · (I0a · S1 · S0 + I1a · S1 · S0 +
I2a · S1 · S0 + I3a · S1 · S0)
Zb = Eb · (I0b · S1 · S0 + I1b · S1 · S0 +
I2b · S1 · S0 + I3b · S1 · S0)
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DS100271-4 |
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Truth Table |
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Select |
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Inputs (a or b) |
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Output |
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Inputs |
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S0 |
S1 |
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E |
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I0 |
I1 |
I2 |
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I3 |
Z |
X |
X |
H |
X |
X |
X |
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X |
L |
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L |
L |
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L |
L |
X |
X |
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X |
L |
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L |
L |
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L |
H |
X |
X |
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X |
H |
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H |
L |
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L |
X |
L |
X |
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X |
L |
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H |
L |
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L |
X |
H |
X |
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X |
H |
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L |
H |
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L |
X |
X |
L |
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X |
L |
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L |
H |
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L |
X |
X |
H |
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X |
H |
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H |
H |
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L |
X |
X |
X |
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L |
L |
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H |
H |
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L |
X |
X |
X |
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H |
H |
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H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
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Logic Diagram
DS100271-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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