NSC 5962R917230MFA, 5962R9172301VEA, 5962R9172301V2A, 5962R9172301MEA, 5962R9172301M2A Datasheet

54AC163

•

54ACT163

Synchronous Presettable Binary Counter

General Description

The ’AC/’ACT163 are high-speed synchronous modulo-16

binary counters.They are synchronously presettable for ap-

plication in programmable dividers and have two types of

Count Enable inputs plus a TerminalCount output for versa-

tility in forming synchronous multistage counters. The ’AC/

’ACT163 has a Synchronous Reset input that overrides

counting and parallelloading and allows theoutputs to besi-

multaneously reset on the rising edge of the clock.

Features

n I

CC

reduced by 50

%

n Synchronous counting and loading

n High-speed synchronous expansion

n Typical count rate of 125 MHz

n Outputs source/sink 24 mA

n ’ACT163 has TTL-compatible inputs

n Standard Microcircuit Drawing (SMD)

— ’AC163: 5962-89582

— ’ACT163: 5962-91723

Logic Symbols

Pin

Names

Description

CEP Count Enable Parallel Input

CET Count Enable Trickle Input

CP Clock Pulse Input

SR

Synchronous Reset Input

P

0

–P

3

Parallel Data Inputs

PE

Parallel Enable Input

Q

0

–Q

3

Flip-Flop Outputs

TC Terminal Count Output

FACT

™

is a trademark of Fairchild Semiconductor Corporation.

DS100275-1

IEEE/IEC

DS100275-2

November 1998

54AC163

•

54ACT163 Synchronous Presettable Binary Counter

© 1998 National Semiconductor Corporation DS100275 www.national.com

Connection Diagrams

Functional Description

The ’AC/’ACT163 counts in modulo-16 binary sequence.

From state 15 (HHHH) it increments to state 0 (LLLL). The

clock inputs of all flip-flops are driven in parallel through a

clock buffer.Thus all changesof the Q outputsoccur as a re-

sult of, and synchronouswith, the LOW-to-HIGH transitionof

the CP input signal. The circuits have four fundamental

modes of operation, inorder of precedence: synchronousre-

set, parallel load, count-up and hold. Four control

inputs—Synchronous Reset (SR), Parallel Enable (PE),

Count Enable Parallel (CEP) and Count Enable Trickle

(CET)—determine the mode of operation, as shown in the

Mode SelectTable. A LOW signal on SR overrides counting

and parallel loading and allowsall outputs togo LOW on the

next rising edgeof CP.ALOW signal on PE overrides count-

ing and allowsinformation on theParallel Data (P

n

) inputs to

be loaded into the flip-flops on the next rising edge of CP.

With PE and SR HIGH,CEP and CETpermit counting when

both are HIGH. Conversely, a LOW signal on either CEP or

CET inhibits counting.

The ’AC/’ACT163 uses D-type edge-triggered flip-flops and

changing the SR, PE, CEP and CET inputs when the CP is

in either state does not cause errors, provided that the rec-

ommended setup and hold times, with respect to the rising

edge of CP, are observed.

The Terminal Count (TC)output is HIGH when CET is HIGH

and counter is in state 15. To implement synchronous multi-

stage counters, the TC outputs can be used with the CEP

and CET inputs in two different ways.

Figure 1

shows the connections for simple ripple carry, in

which the clockperiod must belonger than the CP to TCde-

lay of the firststage,plus the cumulative CETtoTC delays of

the intermediate stages, plus the CET to CP setup time of

the last stage.Thistotal delay plussetup time sets the upper

limit on clock frequency. For fasterclock rates, the carry loo-

kahead connections shown in

Figure 2

are recommended. In

this scheme theripple delay throughthe intermediate stages

commences with the same clock that causes the first stage

to tick over from max to min in the Up mode, or min to max

in the Down mode, to start its final cycle. Since this final

cycle takes 16 clocks to complete, there is plenty of time for

the ripple to progress through the intermediate stages. The

critical timing that limits the clock period is the CP to TC de-

lay of the first stage plus the CEP to CP setup time of the last

stage. The TC output is subject to decoding spikes due to in-

ternal race conditions and is therefore not recommended for

use as a clock or asynchronous reset for flip-flops, registers

or counters.

Logic Equations: Count Enable

=

CEP

•

CET

•

PE

TC

=

Q

0

•

Q

1

•

Q

2

•

Q

3

•

CET

Mode Select Table

SR PE CET CEP Action on the Rising

Clock Edge (

N

)

L X X X Reset (Clear)

H L X X Load (P

n

→

Q

n

)

H H H H Count (Increment)

H H L X No Change (Hold)

H H X L No Change (Hold)

H

=

HIGH Voltage Level

L

=

LOW Voltage Level

X

=

Immaterial

State Diagram

Pin Assignment

for DIP and Flatpak

DS100275-3

Pin Assignment

for LCC

DS100275-4

DS100275-5

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State Diagram (Continued)

DS100275-8

FIGURE 1.

DS100275-9

FIGURE 2.

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Block Diagram

DS100275-6

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

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