NSC 5962R8973501VSA, 5962R8973501VRA, 5962R8973501V2A, 5962R8973501SA, 5962R8973501RA Datasheet
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August 1998
54ACTQ273
Quiet Series Octal D Flip-Flop
General Description
The ACTQ273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) input load and reset (clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's Q output.
All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements.
The ACTQ utilizes NSC Quiet Series technology to guarantee quiet output switching and improved dynamic threshold
performance. FACT Quiet Series™ features GTO™ output control and undershoot corrector in addition to a split ground bus for superior performance.
Features
nICC reduced by 50%
nGuaranteed simultaneous switching noise level and dynamic threshold performance
nImproved latch-up immunity
nBuffered common clock and asynchronous master reset
nOutputs source/sink 24 mA
nFaster prop delays than the standard 'AC/'ACT273
n4 kV minimum ESD immunity
nStandard Microcircuit Drawing (SMD) 5962-89735
Logic Symbols
IEEE/IEC
DS100240-1
DS100240-2
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Pin Names |
Description |
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D0±D7 |
Data Inputs |
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Master Reset |
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MR |
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CP |
Clock Pulse Input |
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Q0±Q7 |
Data Outputs |
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GTO™ is a trademark of National Semiconductor Corporation.
FACT® is a registered trademark of Fairchild Semiconductor Corporation.
FACT Quiet Series™ is a trademark of Fairchild Semiconductor Corporation.
Flop-Flip D Octal Series Quiet 54ACTQ273
© 1998 National Semiconductor Corporation |
DS100240 |
www.national.com |
Connection Diagrams
Pin Assignment |
Pin Assignment |
for DIP and Flatpak |
for LCC |
DS100240-4
DS100240-3
Mode Select-Function Table
Operating Mode |
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Inputs |
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Outputs |
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CP |
Dn |
Qn |
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MR |
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Reset (Clear) |
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L |
X |
X |
L |
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Load ª1º |
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H |
N |
H |
H |
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Load ª0º |
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H |
N |
L |
L |
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Note 1: H = HIGH Voltage Level
Note 2: L = LOW Voltage Level
Note 3: X = Immaterial
Note 4: N = LOW-to-HIGH Transition
Logic Diagram
DS100240-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2 |
Absolute Maximum Ratings (Note 5)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.
Supply Voltage (VCC) |
−0.5V to +7.0V |
DC Input Diode Current (IIK) |
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VI = −0.5V |
−20 mA |
VI = VCC + 0.5V |
+20 mA |
DC Input Voltage (VI) |
−0.5V to V CC + 0.5V |
DC Output Diode Current (IOK) |
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VO = −0.5V |
−20 mA |
VO = VCC + 0.5V |
+20 mA |
DC Output Voltage (VO) |
−0.5V to V CC + 0.5V |
DC Output Source |
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or Sink Current (IO) |
±50 mA |
DC VCC or Ground Current |
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per Output Pin (ICC or IGND) |
±50 mA |
Storage Temperature (TSTG) |
−65ÊC to +150ÊC |
DC Latch-up Source or |
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Sink Current |
±300 mA |
Junction Temperature (TJ) |
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CDIP |
175ÊC |
Recommended Operating
Conditions
Supply Voltage (VCC) |
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'ACTQ |
4.5V to 5.5V |
Input Voltage (VI) |
0V to VCC |
Output Voltage (VO) |
0V to VCC |
Operating Temperature (TA) |
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54ACTQ |
−55ÊC to +125ÊC |
Minimum Input Edge Rate V/ |
t |
'ACTQ Devices |
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VIN from 0.8V to 2.0V |
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VCC @ 4.5V, 5.5V |
125 mV/ns |
Note 5: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of FACT® circuits outside databook specifications.
Note 6: All commercial packaging is not recommended for applications requiring greater than 2000 temperature cycles from −40ÊC to +125ÊC.
DC Characteristics for 'ACTQ Family Devices
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54ACTQ |
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Symbol |
Parameter |
VCC |
TA = −55ÊC |
Units |
Conditions |
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(V) |
to +125ÊC |
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Guaranteed Limits |
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VIH |
Minimum High Level |
4.5 |
2.0 |
V |
VOUT = 0.1V |
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Input Voltage |
5.5 |
2.0 |
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or VCC − 0.1V |
VIL |
Maximum Low Level |
4.5 |
0.8 |
V |
VOUT = 0.1V |
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Input Voltage |
5.5 |
0.8 |
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or VCC − 0.1V |
VOH |
Minimum High Level |
4.5 |
4.4 |
V |
IOUT = −50 µA |
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Output Voltage |
5.5 |
5.4 |
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(Note 7) |
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VIN = VIL or VIH |
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4.5 |
3.7 |
V |
IOH = −24 mA |
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5.5 |
4.7 |
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IOH = −24 mA |
VOL |
Maximum Low Level |
4.5 |
0.1 |
V |
IOUT = 50 µA |
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Output Voltage |
5.5 |
0.1 |
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(Note 7) |
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VIN = VIL or VIH |
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4.5 |
0.50 |
V |
IOL = 24 mA |
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5.5 |
0.50 |
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IOL = 24 mA |
IIN |
Maximum Input |
5.5 |
±1.0 |
µA |
VI = VCC, GND |
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Leakage Current |
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ICCT |
Maximum |
5.5 |
1.6 |
mA |
VI = VCC − 2.1V |
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ICC/Input |
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IOLD |
Minimum Dynamic |
5.5 |
50 |
mA |
VOLD = 1.65V Max |
IOHD |
Output Current (Note 8) |
5.5 |
−50 |
mA |
V OHD = 3.85V Min |
ICC |
Maximum Quiescent |
5.5 |
80.0 |
µA |
VIN = VCC |
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Supply Current |
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or GND (Note 9) |
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3 |
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