NSC 5962R9218901VSA, 5962R9218901VRA, 5962R9218901V2A, 5962R9218901M2A, 5962-9218901MSA Datasheet
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August 1998
54ACQ374 · 54ACTQ374
Quiet Series Octal D Flip-Flop with TRI-STATE® Outputs
General Description
The 'ACQ/'ACTQ374 is a high-speed, low-power octal D-type flip-flop featuring separate D-type inputs for each flip-flop and TRI-STATE outputs for bus-oriented applications. A buffered Clock (CP) and Output Enable (OE) are common to all flip-flops.
The 'ACQ/'ACTQ374 utilizes Quiet Series technology to guarantee quiet output switching and improve dynamic threshold performance. FACT Quiet Series™ features GTO™ output control and undershoot corrector in addition to a split ground bus for superior performance.
nGuaranteed simultaneous switching noise level and dynamic threshold performance
nImproved latch-up immunity
nBuffered positive edge-triggered clock
nTRI-STATE outputs drive bus lines or buffer memory address registers
nOutputs source/sink 24 mA
nFaster prop delays than the standard 'AC/'ACT374
n4 kV minimum ESD immunity
nStandard Military Drawing (SMD)
Ð'ACTQ374: 5962-92189
Ð'ACQ374: 5962-92179
Features
n ICC and IOZ reduced by 50%
Logic Symbols |
Connection Diagrams |
Pin Assignment for DIP and Flatpak
DS100239-1
IEEE/IEC
DS100239-3
Pin Assignment for LCC
DS100239-2
DS100239-4
GTO™ is a trademark of National Semiconductor Corporation.
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
FACT® is a registered trademark of Fairchild Semiconductor Corporation.
FACT Quiet Series™ is a trademark of Fairchild Semiconductor Corporation.
Outputs STATE-TRI with Flop-Flip D Octal Series Quiet 54ACTQ374 · 54ACQ374
© 1998 National Semiconductor Corporation |
DS100239 |
www.national.com |
Connection Diagrams (Continued)
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Pin Names |
Description |
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D0±D7 |
Data Inputs |
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CP |
Clock Pulse Input |
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TRI-STATE Output Enable Input |
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OE |
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O0±O7 |
TRI-STATE Outputs |
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Functional Description
The 'ACQ/'ACTQ374 consists of eight edge-triggered flip-flops with individual D-type inputs and TRI-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transition. With the Output Enable (OE) LOW, the contents of the eight flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops.
Truth Table
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Inputs |
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Outputs |
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Dn |
CP |
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OE |
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On |
H |
N |
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L |
H |
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L |
N |
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L |
L |
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X |
X |
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H |
Z |
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H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
N = LOW-to-HIGH Transition
Logic Diagram
DS100239-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2 |
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.
Supply Voltage (VCC) |
−0.5V to +7.0V |
DC Input Diode Current (IIK) |
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VI = −0.5V |
−20 mA |
VI = VCC + 0.5V |
+20 mA |
DC Input Voltage (VI) |
−0.5V to V CC + 0.5V |
DC Output Diode Current (IOK) |
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VO = −0.5V |
−20 mA |
VO = VCC + 0.5V |
+20 mA |
DC Output Voltage (VO) |
−0.5V to V CC + 0.5V |
DC Output Source |
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or Sink Current (IO) |
±50 mA |
DC VCC or Ground Current |
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per Output Pin (ICC or IGND) |
±50 mA |
Storage Temperature (TSTG) |
−65ÊC to +150ÊC |
DC Latch-Up Source or Sink Current |
±300 mA |
Junction Temperature (TJ) |
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CDIP |
175ÊC |
Recommended Operating
Conditions
Supply Voltage (VCC) |
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'ACQ |
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2.0V to 6.0V |
'ACTQ |
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4.5V to 5.5V |
Input Voltage (VI) |
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0V to VCC |
Output Voltage (VO) |
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0V to VCC |
Operating Temperature (TA) |
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54ACQ/ACTQ |
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−55ÊC to +125ÊC |
Minimum Input Edge Rate |
V/ |
t |
'ACQ Devices |
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VIN from 30% to 70% of VCC |
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VCC @ 3.0V, 4.5V, 5.5V |
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125 mV/ns |
Minimum Input Edge Rate |
V/ |
t |
'ACTQ devices |
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VIN from 0.8V to 2.0V |
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VCC @ 4.5V, 5.5V |
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125 mV/ns |
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of FACT® circuits outside databook specifications.
Note 2: All commercial packaging is not recommended for applications requiring greater than 2000 temperature cycles from −40ÊC to +125ÊC.
DC Characteristics for 'ACQ Family Devices
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54ACQ |
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Symbol |
Parameter |
VCC |
TA = −55ÊC to +125ÊC |
Units |
Conditions |
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(V) |
Guaranteed Limits |
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VIH |
Minimum High Level |
3.0 |
2.1 |
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VOUT = 0.1V |
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Input Voltage |
4.5 |
3.15 |
V |
or VCC − 0.1V |
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5.5 |
3.85 |
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VIL |
Maximum Low Level |
3.0 |
0.9 |
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VOUT = 0.1V |
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Input Voltage |
4.5 |
1.35 |
V |
or VCC − 0.1V |
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5.5 |
1.65 |
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VOH |
Minimum High Level |
3.0 |
2.9 |
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IOUT = −50 µA |
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Output Voltage |
4.5 |
4.4 |
V |
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5.5 |
5.4 |
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(Note 3) |
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VIN = VIL or VIH |
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3.0 |
2.4 |
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IOH = −12 mA |
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4.5 |
3.7 |
V |
IOH = −24 mA |
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5.5 |
4.7 |
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IOH = −24 mA |
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VOL |
Maximum Low Level |
3.0 |
0.1 |
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IOUT = 50 µA |
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Output Voltage |
4.5 |
0.1 |
V |
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5.5 |
0.1 |
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(Note 3) |
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3.0 |
0.50 |
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IOL = 12 mA |
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4.5 |
0.50 |
V |
IOL = 24 mA |
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5.5 |
0.50 |
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IOL = 24 mA |
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IIN |
Maximum Input |
5.5 |
±1.0 |
µA |
VI = VCC, GND |
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Leakage Current |
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(Note 5) |
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(Note 4) |
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IOLD |
Minimum Dynamic |
5.5 |
50 |
mA |
VOLD = 1.65V Max |
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Output Current |
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IOHD |
5.5 |
−50 |
mA |
V OHD = 3.85V Min |
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