August 1998
54ACQ573 · 54ACTQ573
Quiet Series Octal Latch with TRI-STATE® Outputs
General Description
The 'ACQ/'ACTQ573 is a high-speed octal latch with buffered common Latch Enable (LE) and buffered common Output Enable (OE) inputs. The 'ACQ/'ACTQ573 is functionally identical to the 'ACQ/'ACTQ373 but with inputs and outputs on opposite sides of the package. The 'ACQ/'ACTQ utilizes NSC Quiet Series technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet Series™ features GTO™ output control and undershoot corrector in addition to a split ground bus for superior performance.
nGuaranteed simultaneous switching noise level and dynamic threshold performance
nImproved latch-up immunity
nInputs and outputs on opposite sides of package allow easy interface with microprocessors
nOutputs source/sink 24 mA
nFaster prop delays than standard 'ACT573
n4 kV minimum ESD immunity
nStandard Microcircuit Drawing (SMD)
Ð'ACTQ573: 5962-92194
Ð'ACQ573: 5962-92180
Features
n ICC and IOZ reduced by 50%
Logic Symbols
IEEE/IEC
DS100242-1
DS100242-2
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Pin Names |
Description |
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D0±D7 |
Data Inputs |
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LE |
Latch Enable Input |
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TRI-STATE Output Enable Input |
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OE |
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O0±O7 |
TRI-STATE Latch Outputs |
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GTO™ is a trademark of National Semiconductor Corporation.
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
FACT® is a registered trademark of Fairchild Semiconductor Corporation.
FACT Quiet Series™ is a trademark of Fairchild Semiconductor Corporation.
Outputs STATE-TRI with Latch Octal Series Quiet 54ACTQ573 · 54ACQ573
© 1998 National Semiconductor Corporation |
DS100242 |
www.national.com |
Connection Diagrams
Pin Assignment for DIP and Flatpak
DS100242-3
Pin Assignment for LCC
DS100242-4
Logic Diagram
Functional Description
The 'ACQ/'ACTQ573 contains eight D-type latches with TRI-STATE output buffers. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The TRI-STATE buffers are controlled by the Output Enable (OE) input. When OE is LOW, the buffers are enabled. When OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches.
Truth Table
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Inputs |
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Outputs |
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OE |
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LE |
D |
On |
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L |
H |
H |
H |
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L |
H |
L |
L |
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L |
L |
X |
O0 |
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H |
X |
X |
Z |
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H = HIGH Voltage
L = LOW Voltage
Z = High Impedance X = Immaterial
O0 = Previous O0 before HIGH-to-LOW transition of Latch Enable
DS100242-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2 |
Absolute Maximum Ratings (Note 2)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.
Supply Voltage (VCC) |
−0.5V to +7.0V |
DC Input Diode Current (IIK) |
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VI = −0.5V |
−20 mA |
VI = VCC + 0.5V |
+20 mA |
DC Input Voltage (VI) |
−0.5V to V CC + 0.5V |
DC Output Diode Current (IOK) |
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VO = −0.5V |
−20 mA |
VO = VCC + 0.5V |
+20 mA |
DC Output Voltage (VO) |
−0.5V to V CC + 0.5V |
DC Output Source |
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or Sink Current (IO) |
±50 mA |
DC VCC or Ground Current |
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per Output Pin (ICC or IGND) |
±50 mA |
Storage Temperature (TSTG) |
−65ÊC to +150ÊC |
DC Latchup Source |
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or Sink Current |
±300 mA |
Junction Temperature (TJ) |
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CDIP |
175ÊC |
Recommended Operating
Conditions
Supply Voltage (VCC) |
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'ACQ |
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2.0V to 6.0V |
'ACTQ |
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4.5V to 5.5V |
Input Voltage (VI) |
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0V to VCC |
Output Voltage (VO) |
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0V to VCC |
Operating Temperature (TA) |
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54ACQ/ACTQ |
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−55ÊC to +125ÊC |
Minimum Input Edge Rate |
V/ |
t |
'ACQ Devices |
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VIN from 30% to 70% of VCC |
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VCC @ 3.0V, 4.5V, 5.5V |
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125 mV/ns |
Minimum Input Edge Rate |
V/ |
t |
'ACTQ Devices |
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VIN from 0.8V to 2.0V |
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VCC @ 4.5V, 5.5V |
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125 mV/ns |
Note 1: All commercial packaging is not recommended for applications requiring greater than 2000 temperature cycles from −40ÊC to +125ÊC.
Note 2: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of FACT® circuits outside databook specifications.
DC Characteristics for 'ACQ Family Devices
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54ACQ |
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Symbol |
Parameter |
VCC |
TA = −55ÊC to +125ÊC |
Units |
Conditions |
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(V) |
Guaranteed Limits |
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VIH |
Minimum High Level |
3.0 |
2.1 |
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VOUT = 0.1V |
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Input Voltage |
4.5 |
3.15 |
V |
or VCC − 0.1V |
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5.5 |
3.85 |
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VIL |
Maximum Low Level |
3.0 |
0.9 |
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VOUT = 0.1V |
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Input Voltage |
4.5 |
1.35 |
V |
or VCC − 0.1V |
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5.5 |
1.65 |
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VOH |
Minimum High Level |
3.0 |
2.9 |
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IOUT = −50 µA |
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Output Voltage |
4.5 |
4.4 |
V |
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5.5 |
5.4 |
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(Note 3) |
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VIN = VIL or VIH |
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3.0 |
2.4 |
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IOH = −12 mA |
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4.5 |
3.7 |
V |
IOH = −24 mA |
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5.5 |
4.7 |
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IOH = −24 mA |
VOL |
Maximum Low Level |
3.0 |
0.1 |
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IOUT = 50 µA |
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Output Voltage |
4.5 |
0.1 |
V |
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5.5 |
0.1 |
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(Note 3) |
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VIN = VIL or VIH |
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3.0 |
0.50 |
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IOL = 12 mA |
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4.5 |
0.50 |
V |
IOL = 24 mA |
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5.5 |
0.50 |
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IOL = 24 mA |
IIN |
Maximum Input |
5.5 |
±1.0 |
µA |
VI = VCC, GND |
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Leakage Current |
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(Note 5) |
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3 |
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