August 1998
54AC253 · 54ACT253
Dual 4-Input Multiplexer with TRI-STATE® Outputs
General Description
The 'AC/'ACT253 is a dual 4-input multiplexer with TRI-STATE outputs. It can select two bits of data from four sources using common select inputs. The outputs may be individually switched to a high impedance state with a HIGH on the respective Output Enable (OE) inputs, allowing the outputs to interface directly with bus oriented systems.
nMultifunction capability
nNoninverting TRI-STATE outputs
nOutputs source/sink 24 mA
n'ACT253 has TTL-compatible inputs
nStandard Military Drawing (SMD)
Ð'AC253: 5962-87693
Ð'ACT253: 5962-87761
Features
n ICC and IOZ reduced by 50%
Logic Diagrams
IEEE/IEC
DS100285-1
DS100285-2
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Pin Names |
Description |
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I0a±I3a |
Side A Data Inputs |
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I0b±I3b |
Side B Data Inputs |
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S0, S1 |
Common Select Inputs |
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a |
Side A Output Enable Input |
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OE |
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Side B Output Enable Input |
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OE |
b |
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Za, Zb |
TRI-STATE Outputs |
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TRI-STATE® is a registered trademark of National Semiconductor Corporation.
FACT® is a registered trademark of Fairchild Semiconductor Corporation.
Outputs STATE-TRI with Multiplexer Input-4 Dual 54ACT253 · 54AC253
© 1998 National Semiconductor Corporation |
DS100285 |
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Connection Diagrams
Pin Assignment |
Pin Assignment |
for DIP and Flatpak |
for LCC |
DS100285-3
Functional Description
The 'AC/'ACT253 contains two identical 4-input multiplexers with TRI-STATE outputs. They select two bits from four sources selected by common Select inputs (S0, S1). The
4-input multiplexers have individual Output Enable (OEa, OEb) inputs which, when HIGH, force the outputs to a high impedance (High Z) state. This device is the logic implementation of a 2-pole, 4-position switch, where the position of the switch is determined by the logic levels supplied to the two select inputs. The logic equations for the outputs are shown:
Za = OEa · (I0a · S1 · S0 + I1a · S1 · S0 +
DS100285-4
I2a · S1 · S0 + I3a · S1 · S0)
Zb = OEb · (I0b · S1 · S0 + I1b · S1 · S0 +
I2b · S1 · S0 + I3b · S1 · S0)
If the outputs of TRI-STATE devices are tied together, all but one device must be in the high impedance state to avoid high currents that would exceed the maximum ratings. Designers should ensure that Output Enable signals to TRI-STATE devices whose outputs are tied together are designed so that there is no overlap.
Truth Table
Select |
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Data Inputs |
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Output |
Outputs |
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Inputs |
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Enable |
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S0 |
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S1 |
I0 |
I1 |
I2 |
I3 |
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OE |
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Z |
X |
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X |
X |
X |
X |
X |
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H |
Z |
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L |
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L |
L |
X |
X |
X |
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L |
L |
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L |
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L |
H |
X |
X |
X |
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L |
H |
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H |
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L |
X |
L |
X |
X |
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L |
L |
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H |
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L |
X |
H |
X |
X |
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L |
H |
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L |
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H |
X |
X |
L |
X |
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L |
L |
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L |
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H |
X |
X |
H |
X |
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L |
H |
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H |
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H |
X |
X |
X |
L |
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L |
L |
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H |
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H |
X |
X |
X |
H |
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L |
H |
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Address Inputs S0 and S1 are common to both sections.
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
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2 |
Logic Diagram
DS100285-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3 |
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