March 2000
ADC12130/ADC12132/ADC12138 Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold
General Description
The ADC12130, ADC12132 and ADC12138 are 12-bit plus sign successive approximation A/D converters with serial I/O and configurable input multiplexer. The ADC12132 and ADC12138 have a 2 and an 8 channel multiplexer, respectively. The differential multiplexer outputs and A/D inputs are available on the MUXOUT1, MUXOUT2, A/DIN1 and A/DIN2 pins. The ADC12130 has a two channel multiplexer with the multiplexer outputs and A/D inputs internally connected. The ADC12130 family is tested with a 5 MHz clock. On request, these A/Ds go through a self calibration process that adjusts linearity, zero and full-scale errors to typically less than ±1 LSB each.
The analog inputs can be configured to operate in various combinations of single-ended, differential, or pseudo-differential modes. A fully differential unipolar analog input range (0V to +5V) can be accommodated with a single +5V supply. In the differential modes, valid outputs are obtained even when the negative inputs are greater than the positive because of the 12-bit plus sign output data format.
The serial I/O is configured to comply with the NSC MICROWIRE™ . For voltage references, see the LM4040 or LM4041.
Features
nSerial I/O (MICROWIRE, SPI and QSPI Compatible)
n2 or 8 channel differential or single-ended multiplexer
nAnalog input sample/hold function
nPower down mode
nProgrammable acquisition time
nVariable digital output word length and format
nNo zero or full scale adjustment required
n0V to 5V analog input range with single 5V power supply
Key Specifications
nResolution: 12-bit plus sign
n12-bit plus sign conversion time: 8.8 µs (max)
n12-bit plus sign throughput time: 14 µs (max)
nIntegral linearity error: ±2 LSB (max)
nSingle supply: 3.3V or 5V ±10%
nPower consumption
Ð 3.3V |
15 mW (max) |
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Ð 3.3V power down |
40 |
µW (typ) |
Ð 5V |
33 mW (max) |
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Ð 5V power down |
100 |
µW (typ) |
Applications
n Pen-based computers n Digitizers
n Global positioning systems
ADC12138 Simplified Block Diagram
DS012079-1
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
COPS™ microcontrollers, HPC™ and MICROWIRE™ are trademarks of National Semiconductor Corporation.
with Converters A/D I/O Serial Sign Plus Bit-12 Calibrating-Self ADC12130/ADC12132/ADC12138
Sample/Hold and MUX
© 2000 National Semiconductor Corporation |
DS012079 |
www.national.com |
ADC12130/ADC12132/ADC12138
Ordering Information
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Industrial Temperature Range |
NS Package Number |
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−40ÊC ≤ TA ≤ +85ÊC |
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ADC12130CIN |
N16E, Dual-In-Line |
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ADC12130CIWM |
M16B, Wide Body SO |
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ADC12132CIMSA |
MSA20, SSOP |
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ADC12138CIN |
N28B, Dual-In-Line |
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ADC12138CIWM |
M28B |
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ADC12138CIMSA |
MSA28, SSOP |
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Connection Diagrams |
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16-Pin Dual-In-Line and |
20-Pin SSOP Package |
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Wide Body SO Packages |
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DS012079-2
Top View
DS012079-47
Top View
28-Pin Dual-In-Line, SSOP and
Wide Body SO Packages
DS012079-3
Top View
www.national.com |
2 |
Pin Descriptions
CCLK |
The clock applied to this input controls the su- |
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cessive approximation conversion time interval |
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and the acquisition time. The rise and fall times |
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of the clock edges should not exceed 1 µs. |
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SCLK |
This is the serial data clock input. The clock |
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applied to this input controls the rate at which |
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the serial data exchange occurs. The rising |
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edge loads the information on the DI pin into |
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the multiplexer address and mode select shift |
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register. This address controls which channel |
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of the analog input multiplexer (MUX) is se- |
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lected and the mode of operation for the A/D. |
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With |
CS |
low, the falling edge of SCLK shifts |
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the data resulting from the previous ADC con- |
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version out on DO, with the exception of the |
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first bit of data. When CS is low continuously, |
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the first bit of the data is clocked out on the ris- |
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ing edge of EOC (end of conversion). When |
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CS is toggled, the falling edge of CS always |
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clocks out the first bit of data. |
CS |
should be |
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brought low when SCLK is low. The rise and |
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fall times of the clock edges should not exceed |
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1 µs. |
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DI |
This is the serial data input pin. The data ap- |
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plied to this pin is shifted by the rising edge of |
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SCLK into the multiplexer address and mode |
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select register. Table 2 through Table 4 show |
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the assignment of the multiplexer address and |
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the mode select data. |
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DO |
The data output pin. This pin is an active push/ |
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pull output when CS is low. When CS is high, |
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this output is TRI-STATE. The A/D conversion |
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result (DB0±DB12) and converter status data |
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are clocked out by the falling edge of SCLK on |
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this pin. The word length and format of this re- |
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sult can vary (see Table 1). The word length |
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and format are controlled by the data shifted |
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into the multiplexer address and mode select |
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register (see Table 4). |
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EOC |
This pin is an active push/pull output and indi- |
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cates the status of the ADC12130/2/8. When |
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low, it signals that the A/D is busy with a con- |
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version, auto-calibration, auto-zero or power |
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down cycle. The rising edge of EOC signals |
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the end of one of these cycles. |
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This is the chip select pin. When a logic low is |
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CS |
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applied to this pin, the rising edge of SCLK |
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shifts the data on DI into the address register. |
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This low also brings DO out of TRI-STATE. |
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With CS low, the falling edge of SCLK shifts |
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the data resulting from the previous ADC con- |
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version out on DO, with the exception of the |
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first bit of data. When CS is low continuously, |
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the first bit of the data is clocked out on the ris- |
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ing edge of EOC (end of conversion). When |
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CS is toggled, the falling edge of CS always |
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clocks out the first bit of data. |
CS |
should be |
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brought low when SCLK is low. The falling |
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edge of CS resets a conversion in progress |
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and starts the sequence for a new conversion. |
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When CS is brought back low during a conver- |
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sion, that conversion is prematurely termi- |
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nated. The data in the output latches may be |
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corrupted. Therefore, when CS is brought back |
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low during a conversion in progress the data output at that time should be ignored. CS may also be left continuously low. In this case it is imperative that the correct number of SCLK pulses be applied to the ADC in order to remain synchronous. After the ADC supply power is applied it expects to see 13 clock pulses for each I/O sequence. The number of clock pulses the ADC expects is the same as the digital output word length. This word length can be modified by the data shifted in on the DO pin. Table 4 details the data required.
DOR |
This is the data output ready pin. This pin is an |
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active push/pull output. It is low when the con- |
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version result is being shifted out and goes |
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high to signal that all the data has been shifted |
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out. |
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A logic low is required on this pin to program |
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CONV |
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any mode or change the ADC's configuration |
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as listed |
in the |
Mode |
Programming |
Table |
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(Table 4) such as 12-bit conversion, Auto Cal, |
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Auto Zero etc. When this pin is high the ADC is |
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placed in the read data only mode. While in the |
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read data only mode, bringing CS low and |
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pulsing SCLK will only clock out on DO any |
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data stored in the ADCs output shift register. |
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The data on DI will be neglected. A new con- |
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version will not be started and the ADC will re- |
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main in the mode and/or configuration previ- |
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ously programmed. Read data only cannot be |
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performed while a conversion, Auto-Cal or |
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Auto-Zero are in progress. |
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PD |
This is the power down pin. When PD is high |
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the A/D is powered down; when PD is low the |
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A/D is powered up. The A/D takes a maximum |
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of 700 µs to power up after the command is |
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given. |
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CH0±CH7 |
These are the analog inputs of the MUX. A |
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channel input is selected by the address infor- |
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mation at the DI pin, which is loaded on the ris- |
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ing edge of SCLK into the address register |
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(see Table 2 and Table 3). |
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The voltage applied to these inputs should not |
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exceed VA+ or go below GND. Exceeding this |
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range on an unselected channel will corrupt |
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the reading of a selected channel. |
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COM |
This pin is another analog input pin. It is used |
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as a pseudo ground when the analog multi- |
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plexer is single-ended. |
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MUXOUT1, |
These |
are |
the |
multiplexer |
output |
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MUXOUT2 |
pins. |
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A/DIN1, |
These are the converter input pins. MUXOUT1 |
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A/DIN2 |
is usually tied to A/DIN1. MUXOUT2 is usually |
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tied to A/DIN2. If external circuitry is placed be- |
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tween MUXOUT1 and A/DIN1, or MUXOUT2 |
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and A/DIN2 it may be necessary to protect |
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these pins. The voltage at these pins should not exceed VA+ or go below AGND (see Figure 5).
VREF+ This is the positive analog voltage reference input. In order to maintain accuracy, the voltage range of VREF (VREF = VREF+ − V REF−) is
ADC12130/ADC12132/ADC12138
3 |
www.national.com |
ADC12130/ADC12132/ADC12138
Pin Descriptions (Continued)
1 VDC to 5.0 VDC and the voltage at VREF+ cannot exceed VA+. See Figure 6 for recom-
mended bypassing.
VREF− The negative voltage reference input. In order to maintain accuracy, the voltage at this pin must not go below GND or exceed VA+. (See
Figure 6).
VA+, VD+ |
These are the analog and digital power supply |
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pins. VA+ and VD+ are not connected together |
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on the chip. These pins should be tied to the |
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same power supply and bypassed separately |
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(see Figure 6). The operating voltage range of |
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VA+ and VD+ is 3.0 VDC to 5.5 VDC. |
DGND |
This is the digital ground pin (see Figure 6). |
AGND |
This is the analog ground pin (see Figure 6). |
www.national.com |
4 |
Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.
Positive Supply Voltage |
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(V+ = VA+ = VD+) |
6.5V |
Voltage at Inputs and Outputs |
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except CH0±CH7 and COM |
−0.3V to V + +0.3V |
Voltage at Analog Inputs |
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CH0±CH7 and COM |
GND −5V to V + +5V |
|VA+ − V D+| |
300 mV |
Input Current at Any Pin (Note 3) |
±30 mA |
Package Input Current (Note 3) |
±120 mA |
Package Dissipation at |
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TA = 25ÊC (Note 4) |
500 mW |
ESD Susceptability (Note 5) |
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Human Body Model |
1500V |
Soldering Information |
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N Packages (10 seconds) |
260ÊC |
SO Package (Note 6): |
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Vapor Phase (60 seconds) |
215ÊC |
Infrared (15 seconds) |
220ÊC |
Storage Temperature −65ÊC to +150ÊC
Operating Ratings (Notes 1, 2)
Operating Temperature Range |
TMIN ≤ TA ≤ TMAX |
ADC12130CIN, ADC12130CIWM, |
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ADC12132CIMSA, |
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ADC12138CIMSA, |
−40ÊC ≤ TA ≤ +85ÊC |
ADC12138CIN, ADC12138CIWM |
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Supply Voltage (V+ = VA+ = VD+) |
+3.0V to +5.5V |
|VA+ − V D+| |
≤ 100 mV |
VREF+ |
0V to VA+ |
VREF− |
0V to V REF+ |
VREF (VREF+ − V REF−) |
1V to V A+ |
VREF Common Mode Voltage Range |
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0.1 VA+ to 0.6 VA+ |
A/DIN1, A/DIN2, MUXOUT1 |
0V to VA+ |
and MUXOUT2 Voltage Range |
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A/D IN Common Mode Voltage |
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Range |
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0V to VA+ |
Converter Electrical Characteristics
The following specifications apply for (V+ = VA+ = VD+ = +5V, VREF+ = +4.096V, and fully differential input with fixed 2.048V |
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common-mode voltage) or (V+ = VA+ = VD+ = 3.3V, VREF+ = 2.5V and fully-differential input with fixed 1.250V |
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+ ≤ |
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common-mode voltage), V |
− = 0V, 12-bit + sign conversion mode, source impedance for analog inputs, V |
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and V |
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REF |
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REF |
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REF |
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25Ω, fCK = fSK = 5 MHz, and 10 (tCK) acquisition time unless otherwise specified. Boldface limits apply for TA = TJ = TMIN |
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to TMAX; all other limits TA = TJ = 25ÊC. (Notes 7, 8, 9) |
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Symbol |
Parameter |
Conditions |
Typical |
Limits |
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Units |
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(Note 10) |
(Note 11) |
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(Limits) |
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STATIC CONVERTER CHARACTERISTICS |
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Resolution |
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12 + sign |
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Bits (min) |
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+ILE |
Positive Integral Linearity Error |
After Auto-Cal (Notes 12, 18) |
±1/2 |
± 2 |
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LSB (max) |
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−ILE |
Negative Integral Linearity Error |
After Auto-Cal (Notes 12, 18) |
±1/2 |
± 2 |
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LSB (max) |
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DNL |
Differential Non-Linearity |
After Auto-Cal |
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± 1.5 |
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LSB (max) |
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Positive Full-Scale Error |
After Auto-Cal (Notes 12, 18) |
±1/2 |
± 3.0 |
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LSB (max) |
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Negative Full-Scale Error |
After Auto-Cal (Notes 12, 18) |
±1/2 |
± 3.0 |
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LSB (max) |
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Offset Error |
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After Auto-Cal (Notes 5, 18) |
±1/2 |
± 2 |
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LSB (max) |
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VIN(+) = VIN(−) = 2.048V |
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DC Common Mode Error |
After Auto-Cal (Note 15) |
±2 |
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LSB (max) |
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TUE |
Total Unadjusted Error |
After Auto-Cal |
±1 |
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LSB |
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(Notes 12, 13, 14) |
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ADC12130/ADC12132/ADC12138
5 |
www.national.com |
ADC12130/ADC12132/ADC12138
Converter Electrical Characteristics
The following specifications apply for (V+ = VA+ = VD+ = +5V, VREF+ = +4.096V, and fully differential input with fixed 2.048V common-mode voltage) or (V+ = VA+ = VD+ = 3.3V, VREF+ = +2.5V and fully-differential input with fixed 1.250V common-mode voltage), VREF− = 0V, 12-bit + sign conversion mode, source impedance for analog inputs, V REF− and V REF+ ≤ 25Ω, fCK = fSK = 5 MHz, and 10 (tCK) acquisition time unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25ÊC. (Notes 7, 8, 9) (Continued)
Symbol |
Parameter |
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Conditions |
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Typical |
Limits |
Units |
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(Note 10) |
(Note 11) |
(Limits) |
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STATIC CONVERTER CHARACTERISTICS (Continued) |
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Multiplexer Channel to Channel |
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±0.05 |
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Matching |
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Power Supply Sensitivity |
V+ = +5V ±10% |
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VREF = +4.096V |
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Offset Error |
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±0.5 |
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+ Full-Scale Error |
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±0.5 |
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LSB |
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− Full-Scale Error |
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±0.5 |
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LSB |
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+ Integral Linearity Error |
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±0.5 |
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− Integral Linearity Error |
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±0.5 |
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LSB |
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UNIPOLAR DYNAMIC CONVERTER CHARACTERISTICS |
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S/(N+D) |
Signal-to-Noise Plus |
f |
= 1 kHz, V |
IN |
= 5 V |
PP |
, V |
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= 5.0V |
69.4 |
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dB |
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IN |
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REF |
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Distortion Ratio |
f |
= 20 kHz, V |
IN |
= 5 V |
PP |
, V |
REF |
+ = 5.0V |
68.3 |
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dB |
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IN |
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fIN = 40 kHz, VIN = 5 VPP, VREF+ = 5.0V |
65.7 |
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dB |
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−3 dB Full Power Bandwidth |
V IN = 5 VPP, where S/(N+D) drops 3 dB |
31 |
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kHz |
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DIFFERENTIAL DYNAMIC CONVERTER CHARACTERISTICS |
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S/(N+D) |
Signal-to-Noise Plus |
f |
= 1 kHz, V |
IN |
= ±5V, V |
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+ = 5.0V |
77.0 |
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dB |
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IN |
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REF |
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Distortion Ratio |
f |
= 20 kHz, V |
IN |
= ±5V, V |
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= 5.0V |
73.9 |
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dB |
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IN |
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REF |
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f |
= 40 kHz, V |
IN |
= ±5V, V |
|
+ |
= 5.0V |
67.0 |
|
dB |
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IN |
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REF |
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−3 dB Full Power Bandwidth |
V IN = ±5V, where S/(N+D) drops 3 dB |
40 |
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kHz |
||||||||||||
Electrical Characteristics
The following specifications apply for (V+ = VA+ = VD+ = +5V, VREF+ = +4.096V, and fully differential input with fixed 2.048V common-mode voltage) or (V+ = VA+ = VD+ = +3.3V, VREF+ = 2.5V and fully-differential input with fixed 1.250V common-mode voltage), VREF− = 0V, 12-bit + sign conversion mode, source impedance for analog inputs, V REF− and V REF+ ≤ 25Ω, fCK = fSK = 5 MHz, and 10 (tCK) acquisition time unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25ÊC. (Notes 7, 8, 9)
Symbol |
Parameter |
Conditions |
Typical |
Limits |
Units |
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|
(Note 10) |
(Note 11) |
(Limits) |
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REFERENCE INPUT, ANALOG INPUTS AND MULTIPLEXER CHARACTERISTICS |
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CREF |
Reference Input Capacitance |
|
85 |
|
pF |
CA/D |
A/DIN1 and A/DIN2 Analog Input |
|
75 |
|
pF |
|
Capacitance |
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|
A/DIN1 and A/DIN2 Analog Input |
VIN = +5.0V or |
±0.1 |
|
µA |
|
Leakage Current |
VIN = 0V |
|
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|
|
CH0±CH7 and COM Input Voltage |
|
GND − 0.05 |
|
V |
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|
VA+ + 0.05 |
|
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CCH |
CH0±CH7 and COM Input |
|
10 |
|
pF |
|
Capacitance |
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CMUXOUT |
MUX Output Capacitance |
|
20 |
|
pF |
|
Off Channel Leakage (Note 16) |
On Channel = 5V and |
−0.01 |
|
µA |
|
CH0±CH7 and COM Pins |
Off Channel = 0V |
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On Channel = 0V and |
0.01 |
|
µA |
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Off Channel = 5V |
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|
www.national.com |
6 |
Electrical Characteristics (Continued)
The following specifications apply for (V+ = VA+ = VD+ = +5V, VREF+ = +4.096V, and fully differential input with fixed 2.048V common-mode voltage) or (V+ = VA+ = VD+ = +3.3V, VREF+ = 2.5V and fully-differential input with fixed 1.250V common-mode voltage), VREF− = 0V, 12-bit + sign conversion mode, source impedance for analog inputs, V REF− and V REF+ ≤ 25Ω, fCK = fSK = 5 MHz, and 10 (tCK) acquisition time unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25ÊC. (Notes 7, 8, 9)
Symbol |
Parameter |
Conditions |
Typical |
Limits |
Units |
|
|
|
(Note 10) |
(Note 11) |
(Limits) |
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REFERENCE INPUT, ANALOG INPUTS AND MULTIPLEXER CHARACTERISTICS |
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||
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|
On Channel Leakage (Note 16) |
On Channel = 5V and |
0.01 |
|
µA |
|
CH0±CH7 and COM Pins |
Off Channel = 0V |
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On Channel = 0V and |
−0.01 |
|
µA |
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Off Channel = 5V |
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MUXOUT1 and MUXOUT2 |
VMUXOUT = 5.0V or |
0.01 |
|
µA |
|
Leakage Current |
VMUXOUT = 0V |
|
|
|
RON |
MUX On Resistance |
VIN = 2.5V and |
850 |
1900 |
Ω (max) |
|
|
VMUXOUT = 2.4V |
|
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|
RON Matching Channel to Channel |
VIN = 2.5V and |
5 |
|
% |
|
|
VMUXOUT = 2.4V |
|
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|
|
Channel to Channel Crosstalk |
VIN = 5 VPP, fIN = 40 kHz |
−72 |
|
dB |
|
MUX Bandwidth |
|
90 |
|
kHz |
|
|
|
|
|
|
DC and Logic Electrical Characteristics
The following specifications apply for (V+ = VA+ = VD+ = +5V, VREF+ = +4.096V, and fully-differential input with fixed 2.048V common-mode voltage) or (V+ = VA+ = VD+ = +3.3V, VREF+ = +2.5V and fully-differential input with fixed 1.250V common-mode voltage), VREF− = 0V, 12-bit + sign conversion mode, source impedance for analog inputs, V REF− and V REF+ ≤ 25Ω, fCK = fSK = 5 MHz, and 10 (tCK) acquisition time unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25ÊC. (Notes 7, 8, 9)
Symbol |
|
|
Parameter |
|
|
|
|
Conditions |
Typical |
V+ = VA+ = |
V+ = VA+ = |
Units |
|||||
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(Note |
VD+ = 3.3V |
VD+ = 5V |
(Limits) |
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10) |
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Limits |
Limits |
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(Note 11) |
(Note 11) |
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CCLK, |
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DI, PD AND SCLK INPUT CHARACTERISTICS |
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CS, |
CONV, |
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VIN(1) |
|
Logical ª1º Input |
VA+ = VD+ = V+ +10% |
|
2.0 |
2.0 |
V (min) |
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Voltage |
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VIN(0) |
|
Logical ª0º Input |
VA+ = VD+ = V+ −10% |
|
0.8 |
0.8 |
V (max) |
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Voltage |
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I |
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|
Logical ª1º Input |
V |
IN |
= V+ |
|
0.005 |
1.0 |
1.0 |
µA (max) |
|||||
IN(1) |
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Current |
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IIN(0) |
|
Logical ª0º Input |
VIN = 0V |
|
−0.005 |
−1.0 |
−1.0 |
µA (min) |
|||||||||
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Current |
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DO, EOC AND |
|
DIGITAL OUTPUT CHARACTERISTICS |
|
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|||||||||||
DOR |
|
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|
|||||||||||||
V |
OUT(1) |
|
Logical ª1º |
V+ = V |
D |
+ = V+ − 10%, |
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A |
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|||
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Output Voltage |
IOUT = −360 µA |
|
2.4 |
2.4 |
V (min) |
||||||||
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VA+ = VD+ = V+ − 10%, |
|
2.9 |
4.25 |
V (min) |
||||
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|
IOUT = −10 µA |
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V |
OUT(0) |
|
Logical ª0º |
V+ = V |
D |
+ = V+ − 10% |
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A |
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|
Output Voltage |
IOUT = 1.6 mA |
|
0.4 |
0.4 |
V (max) |
||||||||
IOUT |
|
TRI-STATE |
VOUT = 0V |
−0.1 |
−3.0 |
−3.0 |
µA (max) |
||||||||||
|
|
|
|
Output Current |
VOUT = V+ |
−0.1 |
3.0 |
3.0 |
|
||||||||
+ISC |
|
Output Short |
VOUT = 0V |
−14 |
|
|
mA |
||||||||||
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Circuit Source |
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Current |
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|
ADC12130/ADC12132/ADC12138
7 |
www.national.com |
ADC12130/ADC12132/ADC12138
DC and Logic Electrical Characteristics (Continued)
The following specifications apply for (V+ = VA+ = VD+ = +5V, VREF+ = +4.096V, and fully-differential input with fixed 2.048V common-mode voltage) or (V+ = VA+ = VD+ = +3.3V, VREF+ = +2.5V and fully-differential input with fixed 1.250V common-mode voltage), VREF− = 0V, 12-bit + sign conversion mode, source impedance for analog inputs, V REF− and V REF+ ≤ 25Ω, fCK = fSK = 5 MHz, and 10 (tCK) acquisition time unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25ÊC. (Notes 7, 8, 9)
Symbol |
Parameter |
|
|
|
Conditions |
Typical |
V+ = VA+ = |
V+ = VA+ = |
Units |
||
|
|
|
|
|
|
|
|
(Note |
VD+ = 3.3V |
VD+ = 5V |
(Limits) |
|
|
|
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|
|
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|
10) |
|
||
|
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|
Limits |
Limits |
|
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||
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|
(Note 11) |
(Note 11) |
|
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|
|
|
DO, EOC AND |
|
DIGITAL OUTPUT CHARACTERISTICS |
|
|
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|
|||||
DOR |
|
|
|
|
|||||||
−I SC |
Output Short |
VOUT = VD+ |
16 |
|
|
mA |
|||||
|
Circuit Sink |
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Current |
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POWER SUPPLY CHARACTERISTICS |
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|||||||
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ID+ |
Digital Supply |
|
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|
1.5 |
2.5 |
mA (max) |
||
|
Current |
|
= HIGH, Powered Down, CCLK on |
600 |
|
|
µA |
||||
|
|
CS |
|
|
|
||||||
|
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|
= HIGH, Powered Down, CCLK off |
20 |
|
|
µA |
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CS |
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IA+ |
Positive Analog |
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3.0 |
4.0 |
mA (max) |
||
|
Supply Current |
|
= HIGH, Powered Down, CCLK on |
10 |
|
|
µA |
||||
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|
CS |
|
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||||||
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= HIGH, Powered Down, CCLK off |
0.1 |
|
|
µA |
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CS |
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|
|||
IREF |
Reference Input |
|
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||
|
Current |
|
CS |
|
= HIGH, Powered Down, CCLK on |
70 |
|
|
µA |
||
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0.1 |
|
|
µA |
||
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|
CS |
= HIGH, Powered Down, CCLK off |
|
|
|||
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|
|
|
AC Electrical Characteristics
The following specifications apply for (V+ = VA+ = VD+ = +5V, VREF+ = +4.096V, and fully-differential input with fixed 2.048V common-mode voltage) or (V+ = VA+ = VD+ = +3.3V, VREF+ = +2.5V and fully-differential input with fixed 1.250V common-mode voltage), VREF− = 0V, 12-bit + sign conversion mode, source impedance for analog inputs, V REF− and V REF+ ≤ 25Ω, fCK = fSK = 5 MHz, and 10 (tCK) acquisition time unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25ÊC. (Note 17)
Symbol |
Parameter |
Conditions |
Typical |
Limits |
Units |
|
|
|
(Note |
(Note |
(Limits) |
|
|
|
10) |
11) |
|
|
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|
|
|
fCK |
Conversion Clock |
|
10 |
5 |
MHz (max) |
|
(CCLK) Frequency |
|
1 |
|
MHz (min) |
|
|
|
|
|
|
fSK |
Serial Data Clock |
|
10 |
5 |
MHz (max) |
|
SCLK Frequency |
|
0 |
|
Hz (min) |
|
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|
Conversion Clock |
|
|
40 |
% (min) |
|
Duty Cycle |
|
|
60 |
% (max) |
|
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|
Serial Data Clock |
|
|
40 |
% (min) |
|
Duty Cycle |
|
|
60 |
% (max) |
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|
tC |
Conversion Time |
12-Bit + Sign or 12-Bit |
44(tCK) |
44(tCK) |
(max) |
|
|
|
|
8.8 |
µs (max) |
|
|
|
|
|
|
www.national.com |
8 |
AC Electrical Characteristics (Continued)
The following specifications apply for (V+ = VA+ = VD+ = +5V, VREF+ = +4.096V, and fully-differential input with fixed 2.048V common-mode voltage) or (V+ = VA+ = VD+ = +3.3V, VREF+ = +2.5V and fully-differential input with fixed 1.250V common-mode voltage), VREF− = 0V, 12-bit + sign conversion mode, source impedance for analog inputs, V REF− and V REF+ ≤ 25Ω, fCK = fSK = 5 MHz, and 10 (tCK) acquisition time unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25ÊC. (Note 17)
Symbol |
|
|
Parameter |
Conditions |
Typical |
Limits |
Units |
|||||
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(Note |
(Note |
(Limits) |
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10) |
11) |
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tA |
|
Acquisition Time |
6 Cycles Programmed |
6(tCK) |
6(tCK) |
(min) |
||||||
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(Note 19) |
|
|
7(tCK) |
(max) |
|||
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1.2 |
µs (min) |
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1.4 |
µs (max) |
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10 Cycles Programmed |
10(tCK) |
10(tCK) |
(min) |
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11(tCK) |
(max) |
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2.0 |
µs (min) |
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2.2 |
µs (max) |
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18 Cycles Programmed |
18(tCK) |
18(tCK) |
(min) |
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19(tCK) |
(max) |
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3.6 |
µs (min) |
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3.8 |
µs (max) |
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34 Cycles Programmed |
34(tCK) |
34(tCK) |
(min) |
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35(tCK) |
(max) |
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6.8 |
µs (min) |
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7.0 |
µs (max) |
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tCAL |
|
Self-Calibration Time |
|
4944(tCK) |
4944(tCK) |
(max) |
||||||
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988.8 |
µs (max) |
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tAZ |
|
Auto-Zero Time |
|
76(tCK) |
76(tCK) |
(max) |
||||||
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15.2 |
µs (max) |
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tSYNC |
|
Self-Calibration or |
|
2(tCK) |
2(tCK) |
(min) |
||||||
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|
|
Auto-Zero Synchronization |
|
|
3(tCK) |
(max) |
|||
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|
Time from DOR |
|
|
0.40 |
µs (min) |
|||
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0.60 |
µs (max) |
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t |
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9(tSK) |
|
||
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|
|
|
DOR High Time when |
CS |
is Low |
|
9(tSK) |
(max) |
|||
DOR |
|
|||||||||||
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|
|
Continuously for Read Data and Software |
|
|
1.8 |
µs (max) |
|||
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Power Up/Down |
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|||||
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t |
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8(tSK) |
8(tSK) |
(max) |
||||
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CONV |
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CONV |
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1.6 |
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AC Electrical Characteristics
The following specifications apply for (V+ = VA+ = VD+ = +5V, VREF+ = +4.096V, and fully-differential input with fixed 2.048V common-mode voltage) or (V+ = VA+ = VD+ = +3.3V, VREF+ = +2.5V and fully-differential input with fixed 1.250V common-mode voltage), VREF− = 0V, 12-bit + sign conversion mode, source impedance for analog inputs, V REF− and V REF+ ≤ 25Ω, fCK = fSK = 5 MHz, and 10 (tCK) acquisition time unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25ÊC. (Note 17) (Continued)
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Conditions |
Typical |
Limits |
Units |
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(Note 10) |
(Note 11) |
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tHPU |
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Hardware Power-Up Time, Time from |
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700 |
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PD Falling Edge to EOC Rising Edge |
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tSPU |
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Software Power-Up Time, Time from |
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Serial Data Clock Falling Edge to |
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700 |
µs (max) |
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EOC Rising Edge |
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tACC |
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Access Time Delay from |
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CS |
Falling Edge to DO Data Valid |
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ADC12130/ADC12132/ADC12138
9 |
www.national.com |
ADC12130/ADC12132/ADC12138
AC Electrical Characteristics (Continued)
The following specifications apply for (V+ = VA+ = VD+ = +5V, VREF+ = +4.096V, and fully-differential input with fixed 2.048V common-mode voltage) or (V+ = VA+ = VD+ = +3.3V, VREF+ = +2.5V and fully-differential input with fixed 1.250V common-mode voltage), VREF− = 0V, 12-bit + sign conversion mode, source impedance for analog inputs, V REF− and V REF+ ≤ 25Ω, fCK = fSK = 5 MHz, and 10 (tCK) acquisition time unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25ÊC. (Note 17) (Continued)
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Typical |
Limits |
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(Limits) |
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tSET-UP |
Set-Up Time of |
CS |
Falling Edge to |
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tDELAY |
Delay from SCLK Falling |
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ns (min) |
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Falling Edge |
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t1H, t0H |
Delay from |
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Rising Edge to |
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tHDI |
DI Hold Time from Serial Data |
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DI Set-Up Time from Serial Data |
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tHDO |
DO Hold Time from Serial Data |
RL = 3k, CL = 100 pF |
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tDDO |
Delay from Serial Data Clock |
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tRDO |
DO Rise Time, TRI-STATE to High |
RL = 3k, CL = 100 pF |
10 |
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DO Rise Time, Low to High |
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tFDO |
DO Fall Time, TRI-STATE to Low |
RL = 3k, CL = 100 pF |
15 |
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DO Fall Time, High to Low |
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15 |
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tCD |
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Falling Edge |
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DOR |
Falling Edge |
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tSD |
Delay from Serial Data Clock Falling |
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80 |
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Rising Edge |
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CIN |
Capacitance of Logic Inputs |
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COUT |
Capacitance of Logic Outputs |
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Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
Note 2: All voltages are measured with respect to GND, unless otherwise specified.
Note 3: When the input voltage (VIN) at any pin exceeds the power supplies (VIN < GND or VIN > VA+ or VD+), the current at that pin should be limited to 30 mA. The 120 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 30 mA to four.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax, θJA and the ambient temperature, TA. The maximum allowable power dissipation at any temperature is PD = (TJmax − T A)/θJA or the number given in the Absolute Maximum Ratings, whichever is lower. For this device, TJmax = 150ÊC. The typical thermal resistance (θJA) of these parts when board mounted follow:
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Thermal |
Part Number |
Resistance |
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θJA |
ADC12130CIN |
53ÊC/W |
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ADC12130CIWM |
70ÊC/W |
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ADC12132CIMSA |
134ÊC/W |
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ADC12138CIN |
40ÊC/W |
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ADC12138CIWM |
50ÊC/W |
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ADC12138CIMSA |
125ÊC/W |
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Note 5: The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin.
Note 6: See AN450 ªSurface Mounting Methods and Their Effect on Product Reliabilityº or the section titled ªSurface Mountº found in any post 1986 National Semiconductor Linear Data Book for other methods of soldering surface mount devices.
www.national.com |
10 |
AC Electrical Characteristics (Continued)
Note 7: Two on-chip diodes are tied to each analog input through a series resistor as shown below. Input voltage magnitude up to 5V above VA+ or 5V below GND will not damage this device. However, errors in the A/D conversion can occur (if these diodes are forward biased by more than 50 mV) if the input voltage magnitude of selected or unselected analog input go above VA+ or below GND by more than 50 mV. As an example, if VA+ is 4.5 VDC, full-scale input voltage must be ≤4.55 VDC to ensure accurate conversions.
DS012079-4
Note 8: To guarantee accuracy, it is required that the VA+ and VD+ be connected together to the same power supply with separate bypass capacitors at each V+ pin.
Note 9: With the test condition for VREF (VREF+ − V REF−) given as +4.096V, the 12-bit LSB is 1.0 mV. For V REF = 2.5V, the 12-bit LSB is 610 µV. Note 10: Typicals are at TJ = TA = 25ÊC and represent most likely parametric norm.
Note 11: Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level).
Note 12: Positive integral linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive full-scale and zero. For negative integral linearity error, the straight line passes through negative full-scale and zero (see Figure 2 and Figure 3).
Note 13: Zero error is a measure of the deviation from the mid-scale voltage (a code of zero), expressed in LSB. It is the average value of the code transitions between −1 to 0 and 0 to +1 (see Figure 4).
Note 14: Total unadjusted error includes offset, full-scale, linearity and multiplexer errors.
Note 15: The DC common-mode error is measured in the differential multiplexer mode with the assigned positive and negative input channels shorted together.
Note 16: Channel leakage current is measured after the channel selection.
Note 17: Timing specifications are tested at the TTL logic levels, VOL = 0.4V for a falling edge and VOL = 2.4V for a rising edge. TRI-STATE output voltage is forced to 1.4V.
Note 18: The ADC12130 family's self-calibration technique ensures linearity and offset errors as specified, but noise inherent in the self-calibration process will result in a maximum repeatability uncertainty of 0.2 LSB.
Note 19: If SCLK and CCLK are driven from the same clock source, then tA is 6, 10, 18 or 34 clock periods minimum and maximum.
Note 20: The ª12-Bit Conversion of Offsetº and ª12-Bit Conversion of Full-Scaleº modes are intended to test the functionality of the device. Therefore, the tputou data from these modes are not an indication of the accuracy of a conversion result.
DS012079-5
FIGURE 1. Transfer Characteristic
ADC12130/ADC12132/ADC12138
11 |
www.national.com |
ADC12130/ADC12132/ADC12138
AC Electrical Characteristics (Continued)
DS012079-6
FIGURE 2. Simplified Error Curve vs Output Code without Auto-Calibration or Auto-Zero Cycles
DS012079-7
FIGURE 3. Simplified Error Curve vs Output Code after Auto-Calibration Cycle
DS012079-8
FIGURE 4. Offset or Zero Error Voltage
www.national.com |
12 |
Typical Performance Characteristics The following curves apply for 12-bit + sign mode after auto-calibration unless otherwise specified.
Linearity Error Change |
Linearity Error Change |
Linearity Error Change |
vs Clock Frequency |
vs Temperature |
vs Reference Voltage |
DS012079-53 DS012079-54 DS012079-55
Linearity Error Change |
Full-Scale Error Change |
Full-Scale Error Change |
vs Supply Voltage |
vs Clock Frequency |
vs Temperature |
DS012079-56 DS012079-57 DS012079-58
Full-Scale Error Change |
Full-Scale Error Change |
Zero Error Change |
vs Reference Voltage |
vs Supply Voltage |
vs Clock Frequency |
DS012079-59 |
DS012079-60 |
DS012079-61 |
ADC12130/ADC12132/ADC12138
13 |
www.national.com |
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