January 1995
54F/74F164A
Serial-In, Parallel-Out Shift Register
General Description
The 'F164A is a high-speed 8-bit serial-in/parallel-out shift register. Serial data is entered through a 2-input AND gate synchronous with the LOW-to-HIGH transition of the clock. The device features an asynchronous Master Reset which clears the register, setting all outputs LOW independent of the clock. The 'F164A is a faster version of the 'F164.
Features
YTypical shift frequency of 90 MHz
YAsynchronous Master Reset
YGated serial data input
YFully synchronous data transfers
YGuaranteed 4000V min ESD protection
Y'F164A is a faster version of the 'F164
Commercial |
Military |
Package |
Package Description |
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Number |
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74F164APC |
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N14A |
14-Lead (0.300× Wide) Molded Dual-In-Line |
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54F164ADM (Note 2) |
J14A |
14-Lead Ceramic Dual-In-Line |
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74F164ASC (Note 1) |
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M14A |
14-Lead (0.150× Wide) Molded Small Outline, JEDEC |
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74F164ASJ (Note 1) |
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M14D |
14-Lead (0.300× Wide) Molded Small Outline, EIAJ |
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74F164AFM (Note 2) |
W14B |
14-Lead Cerpack |
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74F164ALM (Note 2) |
E20A |
20-Lead Ceramic Leadless Chip Carrier, Type C |
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Note 1: Devices also available in 13× reel. Use suffix e SCX and SJX.
Note 2: Military grade device with environmental and burn-in processing. Use suffix e DMQB, FMQB and LMQB.
Logic Symbols
IEEE/IEC
TL/F/10613 ± 1
TL/F/10613 ± 4
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
Register Shift Out-Parallel In,-Serial 54F/74F164A
C1995 National Semiconductor Corporation |
TL/F/10613 |
RRD-B30M75/Printed in U. S. A. |
Connection Diagrams
Pin Assignment for |
Pin Assignment |
DIP, SOIC and Flatpak |
for LCC |
TL/F/10613 ± 2
TL/F/10613 ± 3
Unit Loading/Fan Out
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54F/74F |
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Pin Names |
Description |
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U.L. |
Input IIH/IIL |
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HIGH/LOW |
Output IOH/IOL |
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A, B |
Data Inputs |
1.0/1.0 |
20 mA/b0.6 mA |
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CP |
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Clock Pulse Input (Active Rising Edge) |
1.0/1.0 |
20 mA/b0.6 mA |
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MR |
Master Reset Input (Active LOW) |
1.0/1.0 |
20 mA/b0.6 mA |
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Q0 ± Q7 |
Outputs |
50/33.3 |
b1 mA/20 mA |
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Functional Description
The 'F164A is an edge-triggered 8-bit shift register with serial data entry and an output from each of the eight stages. Data is entered serially through one of two inputs (A or B); either of these inputs can be used as an active HIGH Enable for data entry through the other input. An unused input must be tied HIGH.
Each LOW-to-HIGH transition on the Clock (CP) input shifts data one place to the right and enters into Q0 the logical AND of the two data inputs (A # B) that existed before the
rising clock edge. A LOW level on the Master Reset (MR) input overrides all other inputs and clears the register asynchronously, forcing all Q outputs LOW.
Mode Select Table
Operating |
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Inputs |
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Outputs |
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Mode |
MR |
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A |
B |
Q0 |
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Q1 |
± Q7 |
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Reset (Clear) |
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L |
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X |
X |
L |
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L-L |
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H |
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l |
l |
L |
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q0 |
± q6 |
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Shift |
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H |
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l |
h |
L |
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q0 |
± q6 |
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H |
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h |
l |
L |
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q0 |
± q6 |
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H |
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h |
h |
H |
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q0 |
± q6 |
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HIGH Voltage Levels LOW Voltage Levels
X e Immaterial
qn e Lower case letters indicate the state of the referenced input or output one setup time prior to the LOW-to-HIGH clock transition.
Logic Diagram
TL/F/10613 ± 5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
2
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Storage Temperature |
b65§C to a150§C |
Ambient Temperature under Bias |
b55§C to a125§C |
Junction Temperature under Bias |
b55§C to a175§C |
Plastic |
b55§C to a150§C |
VCC Pin Potential to |
b0.5V to a7.0V |
Ground Pin |
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Input Voltage (Note 2) |
b0.5V to a7.0V |
Input Current (Note 2) |
b30 mA to a5.0 mA |
Voltage Applied to Output |
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in HIGH State (with VCC e 0V) |
b0.5V to VCC |
Standard Output |
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TRI-STATEÉ Output |
b0.5V to a5.5V |
Current Applied to Output |
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in LOW State (Max) |
twice the rated IOL (mA) |
ESD Last Passing Voltage (Min) |
4000V |
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
Recommended Operating
Conditions
Free Air Ambient Temperature |
b55§C to a125§C |
Military |
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Commercial |
0§C to a70§C |
Supply Voltage |
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Military |
a4.5V to a5.5V |
Commercial |
a4.5V to a5.5V |
DC Electrical Characteristics
Symbol |
Parameter |
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54F/74F |
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Units |
VCC |
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Conditions |
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Min Typ |
Max |
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VIH |
Input HIGH Voltage |
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2.0 |
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V |
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Recognized as a HIGH Signal |
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VIL |
Input LOW Voltage |
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0.8 |
V |
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Recognized as a LOW Signal |
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VCD |
Input Clamp Diode Voltage |
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b1.2 |
V |
Min |
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IIN e b18 mA |
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VOH |
Output HIGH |
54F |
10% VCC |
2.5 |
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IOH e b1 mA |
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Voltage |
74F |
10% VCC |
2.5 |
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V |
Min |
IOH e b1 mA |
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74F |
5% VCC |
2.7 |
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IOH e b1 mA |
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VOL |
Output LOW |
54F |
10% VCC |
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0.5 |
V |
Min |
IOL e 20 mA |
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Voltage |
74F |
10% VCC |
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0.5 |
IOL e 20 mA |
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IIH |
Input HIGH |
54F |
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20.0 |
mA |
Max |
VIN e 2.7V |
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Current |
74F |
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5.0 |
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IBVI |
Input HIGH Current |
54F |
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100 |
mA |
Max |
VIN e 7.0V |
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Breakdown Test |
74F |
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7.0 |
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ICEX |
Output HIGH |
54F |
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250 |
mA |
Max |
VOUT e VCC |
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Leakage Current |
74F |
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50 |
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VID |
Input Leakage |
74F |
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4.75 |
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V |
0.0 |
IID e 1.9 mA |
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Test |
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All other pins grounded |
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IOD |
Output Leakage |
74F |
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3.75 |
mA |
0.0 |
VIOD e 150 mV |
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Circuit Current |
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All other pins grounded |
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IIL |
Input LOW Current |
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b0.6 |
mA |
Max |
VIN e 0.5V |
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IOS |
Output Short-Circuit Current |
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b60 |
b150 |
mA |
Max |
VOUT e 0V |
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ICC |
Power Supply Current |
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35 |
55 |
mA |
Max |
CP e HIGH |
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MR e GND, A, B e GND |
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