MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document by MCM69P735/D
Product Preview |
MCM69P735 |
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128K x 36 Bit Pipelined
BurstRAM Synchronous
Fast Static RAM
The MCM69P735 is a 4M bit synchronous fast static RAM designed to provide a burstable, high performance, secondary cache for the PowerPC and other high performance microprocessors. It is organized as 128K words of 36 bits each. This device integrates input registers, an output register, a 2±bit address counter, and a high speed SRAM onto a single monolithic circuit for reduced parts count in cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K).
Addresses (SA), data inputs (DQx), and all control signals except output enable (G) and linear burst order (LBO) are clock (K) controlled through positive± edge±triggered noninverting registers.
Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst addresses can be generated internally by the MCM69P735 (burst sequence operates in linear or interleaved mode dependent upon the state of LBO) and controlled by the burst address advance (ADV) input pin.
Write cycles are internally self±timed and are initiated by the rising edge of the clock (K) input. This feature eliminates complex off±chip write pulse generation and provides increased timing flexibility for incoming signals.
Synchronous byte write (SBx), synchronous global write (SGW), and synchronous write enable (SW) are provided to allow writes to either individual bytes or to all bytes. The four bytes are designated as ªaº, ªbº, ªcº, and ªdº.controlsSBa DQa, SBb controls DQb, etc. Individual bytes are written if the selected byte writes SBx are asserted with SW. All bytes are written if either SGW is asserted or if all SBx and SW are asserted.
For read cycles, pipelined SRAMs output data is temporarily stored by an edge±triggered output register and then released to the output buffers at the next rising edge of clock (K).
The MCM69P735 operates from a 3.3 V core power supply and all outputs operate on a 3.3 V or 2.5 V power supply. All inputs and outputs are JEDEC standard JESD8±5 compatible.
• MCM69P735 Speed Options
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Pipelined |
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Speed |
tKHKH |
tKHQV |
Setup |
Hold |
IDD |
Pkg |
200 MHz |
5 ns |
2.5 ns |
0.5 ns |
1 ns |
475 mA |
PBGA |
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180 MHz |
5.5 ns |
3.0 ns |
0.5 ns |
1 ns |
450 mA |
PBGA |
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166 MHz |
6 ns |
3.5 ns |
0.5 ns |
1 ns |
425 mA |
PBGA |
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•3.3 V + 10%, ± 5% Core Power Supply, Operates with a 3.3 V or 2.5 V I/O Supply
•ADSP, ADSC, and ADV Burst Control Pins
•Selectable Burst Sequencing Order (Linear/Interleaved)
•Single±Cycle Deselect Timing
•Internally Self±Timed Write Cycle
•Byte Write and Global Write Control
•PB1 Version 2.0 Compatible
•JEDEC Standard 119±Pin PBGA Package
BurstRAM is a trademark of Motorola, Inc.
The PowerPC name is a trademark of IBM Corp., used under license therefrom.
ZP PACKAGE
PBGA
CASE 999±01
This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice.
6/10/97
MOTOROLA FAST SRAM |
MCM69P735 |
Motorola, Inc. 1997 |
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1 |
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FUNCTIONAL BLOCK DIAGRAM |
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LBO |
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ADV |
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K |
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BURST |
2 |
17 |
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ADSC |
K2 |
COUNTER |
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CLR |
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ADSP |
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2 |
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SA |
ADDRESS |
17 |
15 |
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SA1 |
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REGISTER |
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SA0 |
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SGW |
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SW |
WRITE |
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REGISTER |
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SBa |
a |
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WRITE |
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REGISTER |
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SBb |
b |
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4 |
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WRITE |
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REGISTER |
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K |
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c |
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SBc |
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WRITE |
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REGISTER |
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SBd |
d |
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K2 |
K |
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SE1 |
ENABLE |
ENABLE |
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SE2 |
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REGISTER |
REGISTER |
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SE3 |
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128K x 36 ARRAY
36 36
DATA±IN DATA±OUT REGISTER REGISTER
G
DQa ± DQd
MCM69P735 |
MOTOROLA FAST SRAM |
2 |
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PIN ASSIGNMENT
1 |
2 |
3 |
4 |
5 |
6 |
7 |
A |
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VDDQ |
VDDQ |
SA |
SA |
ADSP |
SA |
SA |
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B |
SE2 |
SA |
ADSC |
SA |
SE3 |
NC |
NC |
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C |
SA |
SA |
VDD |
SA |
SA |
NC |
NC |
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D |
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VSS |
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VSS |
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DQb |
DQc |
DQc |
NC |
DQb |
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E |
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DQb |
DQc |
DQc |
VSS |
SE1 |
VSS |
DQb |
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F |
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VSS |
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VSS |
DQb |
VDDQ |
VDDQ |
DQc |
G |
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G |
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ADV |
SBb |
DQb |
DQb |
DQc |
DQc |
SBc |
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H |
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VSS |
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VSS |
DQb |
DQb |
DQc |
DQc |
SGW |
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J |
VDD |
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VDD |
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VDD |
VDDQ |
VDDQ |
NC |
NC |
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K |
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VSS |
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VSS |
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DQa |
DQd |
DQd |
K |
DQa |
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L |
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NC |
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DQa |
DQd |
DQd |
SBd |
SBa |
DQa |
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M |
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SW |
VSS |
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VDDQ |
VDDQ |
DQd |
VSS |
DQa |
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N |
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VSS |
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VSS |
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DQa |
DQd |
DQd |
SA1 |
DQa |
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P |
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VSS |
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VSS |
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DQd |
DQd |
SA0 |
DQa |
DQa |
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R |
SA |
LBO |
VDD |
NC |
SA |
NC |
NC |
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T |
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NC |
NC |
NC |
SA |
SA |
SA |
NC |
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U |
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NC |
VDDQ |
VDDQ |
NC |
NC |
NC |
NC |
TOP VIEW 119 BUMP PBGA
Not to Scale
MOTOROLA FAST SRAM |
MCM69P735 |
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3 |
PBGA PIN DESCRIPTIONS
Pin Locations |
Symbol |
Type |
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Description |
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4B |
ADSC |
Input |
Synchronous Address Status Controller: Active low, interrupts any |
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ongoing burst and latches a new external address. Used to initiate a |
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READ, WRITE, or chip deselect. |
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4A |
ADSP |
Input |
Synchronous Address Status Processor: Active low, interrupts any |
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ongoing burst and latches a new external address used to initiate a new |
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READ or chip deselect (exception Ð chip deselect does not occur |
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when ADSP is asserted and SE1 is high). |
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4G |
ADV |
Input |
Synchronous Address Advance: Increments address count in |
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accordance with counter type selected (linear/interleaved). |
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(a) 6K, 7K, 6L, 7L, 6M, 6N, 7N, 6P, 7P |
DQx |
I/O |
Synchronous Data I/O: ªxº refers to the byte being read or written |
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(b) 6D, 7D, 6E, 7E, 6F, 6G, 7G, 6H, 7H |
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(byte a, b, c, d). |
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(c) 1D, 2D, 1E, 2E, 2F, 1G, 2G, 1H, 2H |
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(d) 1K, 2K, 1L, 2L, 2M, 1N, 2N, 1P, 2P |
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4F |
G |
Input |
Asynchronous Output Enable Input: |
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Low Ð enables output buffers (DQx pins). |
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High Ð DQx pins are high impedance. |
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4K |
K |
Input |
Clock: This signal registers the address, data in, and all control signals |
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except G and LBO. |
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3R |
LBO |
Input |
Linear Burst Order Input: This pin must remain in steady state (this |
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signal not registered or latched). It must be tied high or low. |
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Low Ð linear burst counter (68K/PowerPC). |
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High Ð interleaved burst counter (486/i960/Pentium). |
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2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C, |
SA |
Input |
Synchronous Address Inputs: These inputs are registered and must |
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5C, 6C, 2R, 6R, 3T, 4T, 5T |
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meet setup and hold times. |
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4N, 4P |
SA1, SA0 |
Input |
Synchronous Address Inputs: These pins must be wired to the two |
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LSBs of the address bus for proper burst operation. These inputs are |
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registered and must meet setup and hold times. |
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5L, 5G, 3G, 3L |
SBx |
Input |
Synchronous Byte Write Inputs: ªxº refers to the byte being written (byte |
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(a) (b) (c) (d) |
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a, b, c, d). SGW overrides SBx. |
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4E |
SE1 |
Input |
Synchronous Chip Enable: Active low to enable chip. |
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Negated high Ð blocks ADSP or deselects chip when ADSC is |
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asserted. |
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2B |
SE2 |
Input |
Synchronous Chip Enable: Active high for depth expansion. |
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6B |
SE3 |
Input |
Synchronous Chip Enable: Active low for depth expansion. |
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4H |
SGW |
Input |
Synchronous Global Write: This signal writes all bytes regardless of the |
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status of the SBx and SW signals. If only byte write signals SBx are |
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being used, tie this pin high. |
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4M |
SW |
Input |
Synchronous Write: This signal writes only those bytes that have been |
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selected using the byte write SBx pins. If only byte write signals SBx |
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are being used, tie this pin low. |
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4C, 2J, 4J, 6J, 4R |
VDD |
Supply |
Core Power Supply. |
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1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U |
VDDQ |
Supply |
I/O Power Supply. |
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3D, 5D, 3E, 5E, 3F, 5F, 3H, 5H, |
VSS |
Supply |
Ground. |
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3K, 5K, 3M, 5M, 3N, 5N, 3P, 5P |
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1B, 7B, 1C, 7C, 4D, 3J, 5J, 4L, 1R, 5R, |
NC |
Ð |
No Connection: There is no connection to the chip. |
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7R, 1T, 2T, 6T, 7T, 2U, 3U, 4U, 5U, 6U |
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MCM69P735 |
MOTOROLA FAST SRAM |
4 |
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TRUTH TABLE (See Notes 1 Through 5)
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Address |
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3 |
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Write 2, 4 |
Next Cycle |
Used |
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SE1 |
SE2 |
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SE3 |
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ADSP |
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ADSC |
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ADV |
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G |
DQx |
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Deselect |
None |
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1 |
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X |
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X |
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X |
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0 |
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X |
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X |
High±Z |
X |
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Deselect |
None |
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0 |
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X |
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1 |
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0 |
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X |
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X |
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X |
High±Z |
X |
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Deselect |
None |
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0 |
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0 |
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X |
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0 |
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X |
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X |
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X |
High±Z |
X |
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Deselect |
None |
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X |
X |
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1 |
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1 |
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0 |
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X |
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X |
High±Z |
X |
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Deselect |
None |
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X |
0 |
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X |
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1 |
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0 |
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X |
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X |
High±Z |
X |
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Begin Read |
External |
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0 |
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1 |
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0 |
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0 |
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X |
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X |
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X |
High±Z |
X5 |
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Begin Read |
External |
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0 |
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1 |
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0 |
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1 |
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0 |
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X |
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X |
High±Z |
READ5 |
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Continue Read |
Next |
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X |
X |
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X |
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1 |
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1 |
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0 |
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1 |
High±Z |
READ |
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Continue Read |
Next |
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X |
X |
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X |
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1 |
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1 |
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0 |
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0 |
DQ |
READ |
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Continue Read |
Next |
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1 |
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X |
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X |
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X |
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1 |
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0 |
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1 |
High±Z |
READ |
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Continue Read |
Next |
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1 |
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X |
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X |
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X |
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1 |
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0 |
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0 |
DQ |
READ |
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Suspend Read |
Current |
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X |
X |
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X |
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1 |
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1 |
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1 |
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1 |
High±Z |
READ |
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Suspend Read |
Current |
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X |
X |
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X |
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1 |
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1 |
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1 |
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0 |
DQ |
READ |
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Suspend Read |
Current |
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1 |
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X |
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X |
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X |
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1 |
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1 |
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1 |
High±Z |
READ |
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Suspend Read |
Current |
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1 |
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X |
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X |
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X |
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1 |
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1 |
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0 |
DQ |
READ |
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Begin Write |
External |
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0 |
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1 |
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0 |
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1 |
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0 |
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X |
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X |
High±Z |
WRITE |
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Continue Write |
Next |
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X |
X |
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X |
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1 |
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1 |
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0 |
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X |
High±Z |
WRITE |
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Continue Write |
Next |
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1 |
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X |
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X |
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X |
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1 |
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0 |
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X |
High±Z |
WRITE |
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Suspend Write |
Current |
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X |
X |
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X |
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1 |
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1 |
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1 |
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X |
High±Z |
WRITE |
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Suspend Write |
Current |
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1 |
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X |
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X |
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X |
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1 |
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1 |
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X |
High±Z |
WRITE |
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NOTES: |
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1.X = don't care. 1 = logic high. 0 = logic low.
2.Write is defined as either (a) any SBx and SW low or (b) SGW is low.
3.G is an asynchronous signal and is not sampled by the clock K. G drives the bus immediately (tGLQX) following G going low.
4.On write cycles that follow read cycles, G must be negated prior to the start of the write cycle to ensure proper write data setup times. G must also remain negated at the completion of the write cycle to ensure proper write data hold times.
5.This read assumes the RAM was previously deselected.
LINEAR BURST ADDRESS TABLE (LBO = VSS)
1st Address (External) |
2nd Address (Internal) |
3rd Address (Internal) |
4th Address (Internal) |
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X . . . |
X00 |
X . |
. . X01 |
X . . . |
X10 |
X . . . |
X11 |
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X . . . |
X01 |
X . |
. . X10 |
X . . . |
X11 |
X . . . |
X00 |
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X . . . |
X10 |
X . |
. . X11 |
X . . . |
X00 |
X . . . |
X01 |
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X . . . |
X11 |
X . |
. . X00 |
X . . . |
X01 |
X . . . |
X10 |
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INTERLEAVED BURST ADDRESS TABLE (LBO = VDD)
1st Address (External) |
2nd Address (Internal) |
3rd Address (Internal) |
4th Address (Internal) |
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X . . . |
X00 |
X . . . |
X01 |
X . . . |
X10 |
X . . . |
X11 |
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X . . . |
X01 |
X . . . |
X00 |
X . . . |
X11 |
X . . . |
X10 |
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X . . . |
X10 |
X . . . |
X11 |
X . . . |
X00 |
X . . . |
X01 |
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X . . . |
X11 |
X . . . |
X10 |
X . . . |
X01 |
X . . . |
X00 |
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WRITE TRUTH TABLE
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Cycle Type |
SGW |
SW |
SBa |
SBb |
SBc |
SBd |
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Read |
H |
H |
X |
X |
X |
X |
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Read |
H |
L |
H |
H |
H |
H |
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Write Byte a |
H |
L |
L |
H |
H |
H |
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Write Byte b |
H |
L |
H |
L |
H |
H |
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Write Byte c |
H |
L |
L |
H |
L |
H |
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Write Byte d |
H |
L |
H |
L |
H |
L |
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Write All Bytes |
H |
L |
L |
L |
L |
L |
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Write All Bytes |
L |
X |
X |
X |
X |
X |
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MOTOROLA FAST SRAM |
MCM69P735 |
|
5 |