Motorola MCM6341ZP10, MCM6341ZP11, MCM6341ZP12, MCM6341ZP15, SCM6341ZP10A Datasheet

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Order this document by MCM6341/D

Advance Information

128K x 24 Bit Static Random

Access Memory

The MCM6341 is a 3,145,728±bit static random access memory organized as 131,072 words of 24 bits. Static design eliminates the need for external clocks or timing strobes.

The MCM6341 is equipped with chip enable (E1, E2, E3) and output enable

(G) pins, allowing for greater system flexibility and eliminating bus contention problems.

The MCM6341 is available in a 119±bump PBGA package.

•Single 3.3 V ± 10% Power Supply

•Fast Access Time: 10/11/12/15 ns

•Equal Address and Chip Enable Access Time

•All Inputs and Outputs are TTL Compatible

•Three±State Outputs

•Power Operation: 280/275/270/260 mA Maximum, Active AC

•Commercial Temperature (0°C to 70°C) and Industrial Temperature (± 40°C to + 85°C) Options

BLOCK DIAGRAM

A
A
A
A
A	ROW
		MEMORY MATRIX
A	DECODER
A
A
A
DQ				COLUMN I/O
	INPUT			COLUMN DECODER
	DATA
	CONTROL
DQ
	A	A	A	A	A	A	A	A
E1								DQ
E2
E3
W								DQ
G

MCM6341

ZP PACKAGE

PBGA

CASE 999±02

PIN NAMES

A . . . . . . . . . . . . . . . . . . . . . . Address Inputs

W . . . . . . . . . . . . . . . . . . . . . . . Write Enable

G . . . . . . . . . . . . . . . . . . . . . Output Enable

E1, E2, E3 . . . . . . . . . . . . . . . . Chip Enable

DQ . . . . . . . . . . . . . . . . . Data Input/Output

NC . . . . . . . . . . . . . . . . . . . . No Connection

VDD . . . . . . . . . . . . . + 3.3 V Power Supply

VSS . . . . . . . . . . . . . . . . . . . . . . . . . Ground

This document contains information on a new product. Specifications and information herein are subject to change without notice.

REV 2 2/18/98

Motorola, Inc. 1998	MCM6341
MOTOROLA FAST SRAM
	1

PIN ASSIGNMENT

		1	2	3	4	5	6	7
	A	NC	A	A	A	A	A	NC
	B	NC	A	A	E1	A	A	NC
	C	DQ	NC	E2	NC	E3	NC	DQ
	D	DQ	VDD	VSS	VSS	VSS	VDD	DQ
	E
		DQ	VSS	VDD	VSS	VDD	VSS	DQ
	F	DQ	VDD	VSS	VSS	VSS	VDD	DQ
	G
		DQ	VSS	VDD	VSS	VDD	VSS	DQ
	H
		DQ	VDD	VSS	VSS	VSS	VDD	DQ
	J	VDD	VSS	VDD	VSS	VDD	VSS	VDD
	K	DQ	VDD	VSS	VSS	VSS	VDD	DQ
	L	DQ	VSS	VDD	VSS	VDD	VSS	DQ
	M
		DQ	VDD	VSS	VSS	VSS	VDD	DQ
	N
		DQ	VSS	VDD	VSS	VDD	VSS	DQ
	P
		DQ	VDD	VSS	VSS	VSS	VDD	DQ
	R	DQ	NC	NC	NC	NC	NC	DQ
	T	NC	A	A	W	A	A	NC
	U	NC	A	A	G	A	A	NC

119±BUMP PBGA

TOP VIEW

MCM6341	MOTOROLA FAST SRAM
2

TRUTH TABLE (X = Don't Care)

E1

E2

E3

G

W

Mode

I/O Pin

Cycle

Current

H

X

X

X

X

Not Selected

High±Z

Ð

ISB1, ISB2

X

L

X

X

X

Not Selected

High±Z

Ð

ISB1, ISB2

X

X

H

X

X

Not Selected

High±Z

Ð

ISB1, ISB2

L

H

L

H

H

Output Disabled

High±Z

Ð

IDDA

L

H

L

L

H

Read

Dout

Read

IDDA

L

H

L

X

L

Write

High±Z

Write

IDDA

ABSOLUTE MAXIMUM RATINGS (See Note)

Rating	Symbol	Value		Unit
Power Supply Voltage Relative to VSS	VDD	± 0.5 to +	5.0	V
Voltage Relative to VSS for Any Pin	Vin, Vout	± 0.5 to VDD + 0.5		V
Except VDD
Output Current (per I/O)	Iout	± 20		mA
Power Dissipation	PD	1.0		W
Temperature Under Bias Commercial	Tbias	± 10 to +	85	°C
Industrial		± 45 to +	90
Storage Temperature Ð Plastic	Tstg	± 55 to + 150		°C

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPER-

ATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.

This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to these high±impedance circuits.

This CMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow of at least 500 linear feet per minute is maintained.

MOTOROLA FAST SRAM	MCM6341
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