Motorola MCM72CB64SG80, MCM72CB64SG100, MCM72CB32SG66, MCM72CB64SG66, MCM72CB32SG80 Datasheet

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Order this document by MCM72CB32/D

256KB and 512KB BurstRAM

Secondary Cache Module for Pentium

The MCM72CB32SG and MCM72CB64SG are designed to provide a burstable, high performance, 256K/512K L2 cache for the Pentium microprocessor. The modules are configured as 32K x 72 and 64K x 72 bits in a 160 pin card edge memory module. The module uses four of Motorola's MCM67C518 or MCM67C618 BiCMOS BurstRAMs.

Bursts can be initiated with either address status processor (ADSP) or address status controller (ADSC). Subsequent burst addresses are generated internal to the BurstRAM by the burst advance (ADV) input pin.

Write cycles are internally self timed and are initiated by the rising edge of the clock (K) input. Eight write enables are provided for byte write control.

The cache family is designed to interface with popular Pentium cache controllers with on board tag.

PD0 ± PD2 are reserved for density and speed identification.

•Pentium±style Burst Counter on Board

•160 Pin Card Edge Module

•Single 5 V ± 5% Power Supply

•All Inputs and Outputs are TTL Compatible

•Three State Outputs

•Byte Parity

•Byte Write Capability

•Fast Module Clock Rates: 66 MHz, 80 MHz, 100 MHz

•Decoupling Capacitors for each Fast Static RAM

•High Quality Multi±Layer FR4 PWB With Separate Power and Ground Planes

•I/Os are 3.3 V Compatible

•Burndy Connector, Part Number: CELP2X80SC3Z48

BurstRAM is a trademark of Motorola.

Pentium is a trademark of Intel Corp.

MCM72CB32

MCM72CB64

160±LEAD CARD EDGE CASE 1113±01 TOP VIEW

1

42

43

80

REV 1 5/95

Motorola, Inc. 1995

PIN ASSIGNMENT

160±LEAD CARD EDGE MODULE

TOP VIEW

			Cache
PD2	PD1	PD0	Size	Module
VSS	VSS	NC	256KB	72CB32SG
VSS	VSS	VSS	512KB	72CB64SG

PIN NAMES

A3 ± A18 . . . . . . .

. . . . . . . . . . . . . . . Address Inputs

K0, K1 . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . Clock

±

Byte Write

W0

W7

E0,

E1

.

. . . .

. . .

. .

. . . . . . . . . . . . . . Module Enable

G0,

G1

.

. . . .

. . .

. .

. . . . . . . Module Output Enable

DQ0 ± DQ63 . . . . .

. . . . . Cache Data Input/Output

DQP0 ± DQP7 . . .

. . . . . . Data Parity Input/Output

Controller Address Status

ADSC0,

ADSC1

ADSP0,

ADSP1

. .

. . . . Processor Address Status

ADV0,

ADV1

. . . . .

. . . . . . . . . . . . . . Burst Advance

PD0 ± PD2 . . . . . .

. . . . . . . . . . . . Presence Detect

VCC5 . . . . . . . . . . .

. . . . . . . . . . + 5 V Power Supply

VSS . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . Ground

*No Connect for MCM72CB32/MCM72CB64

**No Connect for MCM72CB32

	VSS		81	1		VSS
DQ63			82	2		DQ62
VCC5			83	3		VCC3*
DQ61			84	4		DQ60
VCC5			85	5		VCC3*
DQ59			86	6		DQ58
DQ57			87	7		DQ56
	VSS		88	8		VSS
DQP7			89	9		DQP6
DQ55			90	10		DQ54
DQ53			91	11		DQ52
DQ51			92	12		DQ50
	VSS		93	13		VSS
DQ49			94	14		DQ48
DQ47			95	15		DQ46
DQ45			96	16		DQ44
DQ43			97	17		DQ42
	VSS		98	18		VSS
DQ41			99	19		DQ40
DQP5			100	20		DQP4
DQ39			101	21		DQ38
DQ37			102	22		DQ36
DQ35			103	23		DQ34
	VSS		104	24		VSS
DQ33			105	25		DQ32
DQ31			106	26		DQ30
DQ29			107	27		DQ28
DQ27			108	28		DQ26
DQ25			109	29		DQ24
	VSS		110	30		VSS
DQP3			111	31		DQP2
DQ23			112	32		DQ22
DQ21			113	33		DQ20
VCC5			114	34		VCC3*
DQ19			115	35		DQ18
	VSS		116	36		VSS
DQ17			117	37		DQ16
VCC5			118	38		VCC3*
DQ15			119	39		DQ14
DQ13			120	40		DQ12
	VSS		121	41		VSS
	DQ11		122	42		DQ10
VCC5			123	43		VCC3*
	DQ9		124	44		DQ8
DQP1			125	45		DQP0
VCC5			126	46		VCC3*
	DQ7		127	47		DQ6
	DQ5		128	48		DQ4
	DQ3		129	49		DQ2
	DQ1		130	50		DQ0
	VSS		131	51		VSS
	A3B		132	52		A3A
	A4B		133	53		A4A
	A5B		134	54		A5A
	A6B		135	55		A6A
	A7		136	56		A8
	VSS		137	57		VSS
	A9		138	58		A10
	A11		139	59		A12
	A13		140	60		A14
	A15		141	61		A16
	A17		142	62		A18**
	VSS		143	63		VSS
	*A19		144	64		PD0
	PD1		145	65		PD2
	K0		146	66		K1
	*K2		147	67		K3*
	VSS		148	68		VSS
	WE7		149	69		WE6
	WE5		150	70		WE4
	WE3		151	71		WE2
	WE1		152	72		WE0
	VSS		153	73		VSS
ADSC1			154	74		ADSC0
	E1		155	75		E0
ADV1			156	76		ADV0
	G1		157	77		G0
VCC5			158	78		VCC3*
ADSP1			159	79		ADSP0
	VSS		160	80		VSS

MCM72CB32•MCM72CB64	MOTOROLA FAST SRAM
2

			64K x 72 BurstRAM MEMORY MODULE BLOCK DIAGRAM
		12	MCM67C618
	A7 ± A18		A4 ± A15	LW	W0
		4
	A3A ± A6A		A0 ± A3
				8
	ADSP0		ADSP
				DQ0 ± DQ7	DQ0 ± DQ7
	ADSC0		ADSC	DQ8	DQP0
	ADV0		ADV	UW	W1
				8	DQ8 ± DQ15
	K0		K	DQ9 ± DQ16
	G0		G	DQ17	DQP1
	E0		E
			MCM67C618
			A4 ± A15	LW	W2
			A0 ± A3	8
			ADSP
				DQ0 ± DQ7	DQ16 ± DQ23
			ADSC	DQ8	DQP2
			ADV	UW	W3
				8	DQ24 ± DQ31
			K	DQ9 ± DQ16
			G	DQ17	DQP3
			E
			MCM67C618
		4	A4 ± A15	LW	W4
	A3B ± A6B		A0 ± A3
				8
	ADSP1		ADSP
				DQ0 ± DQ7	DQ32 ± DQ39
	ADSC1		ADSC	DQ8	DQP4
	ADV1		ADV	UW	W5
				8	DQ40 ± DQ47
	K1		K	DQ9 ± DQ16
	G1		G	DQ17	DQP5
	E1		E
			MCM67C618
			A4 ± A15	LW	W6
			A0 ± A3	8
			ADSP
				DQ0 ± DQ7	DQ48 ± DQ55
			ADSC	DQ8	DQP6
			ADV	UW	W7
				8	DQ56 ± DQ63
			K	DQ9 ± DQ16
			G	DQ17	DQP7
			E

MOTOROLA FAST SRAM	MCM72CB32•MCM72CB64
	3

		32K x 72 BurstRAM MEMORY MODULE BLOCK DIAGRAM
	A18	NC	MCM67C518
	A7 ± A17	11	A4 ± A14	LW	W0
		4
	A3A ± A6A		A0 ± A3
				8
	ADSP0		ADSP
				DQ0 ± DQ7	DQ0 ± DQ7
	ADSC0		ADSC	DQ8	DQP0
	ADV0		ADV	UW	W1
				8	DQ8 ± DQ15
	K0		K	DQ9 ± DQ16
	G0		G	DQ17	DQP1
	E0		E
			MCM67C518
			A4 ± A14	LW	W2
			A0 ± A3	8
			ADSP
				DQ0 ± DQ7	DQ16 ± DQ23
			ADSC	DQ8	DQP2
			ADV	UW	W3
				8	DQ24 ± DQ31
			K	DQ9 ± DQ16
			G	DQ17	DQP3
			E
			MCM67C518
		4	A4 ± A14	LW	W4
	A3B ± A6B		A0 ± A3
				8
	ADSP1		ADSP
				DQ0 ± DQ7	DQ32 ± DQ39
	ADSC1		ADSC	DQ8	DQP4
	ADV1		ADV	UW	W5
				8	DQ40 ± DQ47
	K1		K	DQ9 ± DQ16
	G1		G	DQ17	DQP5
	E1		E
			MCM67C518
			A4 ± A14	LW	W6
			A0 ± A3	8
			ADSP
				DQ0 ± DQ7	DQ48 ± DQ55
			ADSC	DQ8	DQP6
			ADV	UW	W7
				8	DQ56 ± DQ63
			K	DQ9 ± DQ16
			G	DQ17	DQP7
			E

MCM72CB32•MCM72CB64	MOTOROLA FAST SRAM
4

	MCM67C618 BLOCK DIAGRAM (See Note)
	ADV	BURST LOGIC
				INTERNAL
K		Q0	A0′	ADDRESS
	BINARY COUNTER	Q1	A0	16	ARRAY
			A1′
					64K	×18
					MEMORY
ADSC	CLR		A1
ADSP
	A1 ± A0		2
			A2 ± A15
A0 ± A15	ADDRESS
	REGISTER			18	9	9
	16
UW	WRITE			DATA±IN
	REGISTER
LW				REGISTERS
E	ENABLE				DATA±OUT
					REGISTERS
	REGISTER
				9	9
						OUTPUT
G						BUFFER
	9
DQ0 ± DQ8
DQ9 ± DQ17	9

NOTE: All registers are positive±edge triggered. The ADSC or ADSP signals control the duration of the burst and the start of the next burst. When ADSP is sampled low, any ongoing burst is interrupted and a read (independent of W and ADSC) is performed using the new external address. Alternatively, an ADSP±initiated two cycle WRITE can be performed by asserting ADSP and a valid address on the first cycle, then negating both ADSP and ADSC and asserting LW and/or UW with valid data on the second cycle (see Single Write Cycle in WRITE CYCLES timing diagram).

When ADSC is sampled low (and ADSP is sampled high), any ongoing burst is interrupted and a read or write (dependent on W) is performed using the new external address. Chip enable (E) is sampled only when a new base address is loaded. After the first cycle of the burst, ADV controls subsequent burst cycles. When ADV is sampled low, the internal address is advanced prior to the operation. When ADV is sampled high, the internal address is not advanced, thus inserting a wait state into the burst sequence accesses. Upon completion of a burst, the address will wrap around to its initial state. See BURST SEQUENCE TABLE. Write refers to either or both byte write enables (LW, UW).

BURST SEQUENCE TABLE (See Note)

External Address	A15 ± A2	A1				A0
1st Burst Address	A15 ± A2	A1
						A0
2nd Burst Address	A15 ± A2					A0
			A1
3rd Burst Address	A15 ± A2
			A1			A0

NOTE: The burst wraps around to its initial state upon completion.

MOTOROLA FAST SRAM	MCM72CB32•MCM72CB64
	5