Motorola MCM72BA64SG66, MCM72BA64SG50, MCM72BA32SG66, MCM72BA32SG60, MCM72BA64SG60 Datasheet

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Order this document by MCM72BA32/D

256KB and 512KB BurstRAM

Secondary Cache Module for Pentium

The MCM72BA32SG and MCM72BA64SG are designed to provide a burstable, high performance, 256K/512K L2 cache for the Pentium microprocessor. The modules are configured as 32K x 72 and 64K x 72 bits in a 136 pin dual readout single inline memory module (DIMM). The module uses four of Motorola's MCM67B518 or MCM67B618 BiCMOS BurstRAMs.

Bursts can be initiated with either address status processor (ADSP) or address status controller (ADSC). Subsequent burst addresses are generated internal to the BurstRAM by the burst advance (ADV) input pin.

Write cycles are internally self timed and are initiated by the rising edge of the clock (K) input. Eight write enables are provided for byte write control.

The cache family is designed to interface with popular Pentium cache controllers with on board TAG.

PD0 ± PD2 are reserved for density and speed identification.

•Pentium±style Burst Counter on Board

•Dual Readout SIMM for Circuit Density

•Single 5 V ± 5% Power Supply

•All Inputs and Outputs are TTL Compatible

•Three State Outputs

•Byte Parity

•Byte Write Capability

•Fast Module Clock Rates: 66 MHz, 60 MHz, 50MHz

•Decoupling Capacitors for each Fast Static RAM

•High Quality Multi±Layer FR4 PWB With Separate Power and Ground Planes

•I/Os are 3.3 V Compatible

MCM72BA32

MCM72BA64

136±LEAD DIMM CASE 1104±01 TOP VIEW

1

34

35

68

BurstRAM is a trademark of Motorola. Pentium is a trademark of Intel Corp.

REV 2 5/95

Motorola, Inc. 1995

PIN ASSIGNMENT 136±LEAD DIMM TOP VIEW

			Cache
PD2	PD1	PD0	Size	Module
VSS	NC	NC	512KB	72BA64SG66/60
VSS	NC	VSS	512KB	72BA64SG50
VSS	VSS	NC	256KB	72BA32SG66/60
VSS	VSS	VSS	256KB	72BA32SG50

PIN NAMES

A0 ± A15 . . . . . . .

. . . . . . . . . . . . . . . Address Inputs

K0, K1 . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . Clock

±

Byte Write

W0

W7

E0,

E1

. . . . . . . . . .

. . . . . . . . . . . . . . Module Enable

G0

,

G1

. . . . . . . . . .

. . . . . . . Module Output Enable

DQ0 ± DQ63 . . . . .

. . . . . Cache Data Input/Output

DQP0 ± DQP7 . . .

. . . . . . Data Parity Input/Output

Controller Address Status

ADSC

ADSP

. . . . . . . . . . .

. . . . Processor Address Status

ADV

. . . . . . . . . . . .

. . . . . . . . . . . . . . Burst Advance

PD0 ± PD2 . . . . . .

. . . . . . . . . . . . Presence Detect

VCC . . . . . . . . . . . .

. . . . . . . . . . + 5 V Power Supply

VSS . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . Ground

* This pin on the MCM72BA32 is a No Connect (NC)

		PD0						1	69		VSS
		PD1						2	70		PD2
		DQ0						3	71		VCC
		DQ1						4	72		DQ2
	VCC							5	73		DQ3
		DQ4						6	74		DQ5
		DQ6						7	75		DQ7
DQP0								8	76		VSS
		DQ8						9	77		DQ9
	DQ10							10	78		DQ11
		VSS						11	79		DQ12
			K0					12	80		VSS
		VSS						13	81		DQ13
	DQ14							14	82		DQ15
	VCC							15	83		DQP1
	DQ16							16	84		VSS
	DQ17							17	85		DQ18
	DQ19							18	86		DQ20
	DQ21							19	87		DQ22
	VCC							20	88		DQ23
	DQP2							21	89		VSS
	DQ24							22	90		DQ25
	DQ26							23	91		DQ27
	DQ28							24	92		DQ29
		VSS						25	93		DQ30
	DQ31							26	94		VSS
	DQP3							27	95
											E0
		VSS						28	96		W1
			W0					29	97
											W3
								30	98
			W2								G0
								31	99
	ADSP										ADSC
								32	100		VSS
		ADV
	VCC							33	101		G1
			W4					34	102		W5
								35	103
			W6								W7
	DQ32							36	104		E1
	DQ33							37	105		DQ34
		VSS						38	106		DQ35
	DQ36							39	107		DQ37
	DQ38							40	108		VCC
	DQ39							41	109		DQP4
	DQ40							42	110		DQ41
	VCC							43	111		DQ42
	DQ43							44	112		DQ44
	DQ45							45	113		VSS
	DQ46							46	114		DQ47
	DQP5							47	115		DQ48
		VSS						48	116		DQ49
			K1					49	117		VSS
		VSS						50	118		DQ50
	DQ52							51	119		DQ51
	DQ53							52	120		DQ54
	DQ55							53	121		DQ56
	DQP6							54	122		VSS
	VCC							55	123		DQ57
	DQ58							56	124		DQ59
	DQ60							57	125		DQ61
	DQ62							58	126		DQ63
	DQP7							59	127		VCC
			A0					60	128		A1
			A2					61	129		A3
			A4					62	130		A5
			A6					63	131		A7
			A8					64	132		NC
		A10						65	133		A9
		A12						66	134		A11
		A14						67	135		A13
		VSS						68	136		A15*

MCM72BA32•MCM72BA64	MOTOROLA FAST SRAM
2

		64K x 72 BurstRAM MEMORY MODULE BLOCK DIAGRAM
	16	MCM67B618
A0 ± A15
		A0 ± A15	LW	W0
			8
ADSP		ADSP	DQ0 ± DQ7	DQ0 ± DQ7
ADSC		ADSC	DQ8	DQP0
ADV		ADV	UW	W1
			8
K0		K	DQ9 ± DQ16	DQ8 ± DQ15
G0		G	DQ17	DQP1
E0		E
		MCM67B618
		A0 ± A15	LW	W2
			8
		ADSP	DQ0 ± DQ7	DQ16 ± DQ23
		ADSC	DQ8	DQP2
		ADV	UW	W3
			8
		K	DQ9 ± DQ16	DQ24 ± DQ31
		G	DQ17	DQP3
		E
		MCM67B618
		A0 ± A15	LW	W4
			8
		ADSP	DQ0 ± DQ7	DQ32 ± DQ39
		ADSC	DQ8	DQP4
		ADV	UW	W5
K1			8
		K	DQ9 ± DQ16	DQ40 ± DQ47
G1		G	DQ17	DQP5
E1		E
		MCM67B618
		A0 ± A15	LW	W6
			8
		ADSP	DQ0 ± DQ7	DQ48 ± DQ55
		ADSC	DQ8	DQP6
		ADV	UW	W7
			8
		K	DQ9 ± DQ16	DQ56 ± DQ63
		G	DQ17	DQP7
		E

MOTOROLA FAST SRAM	MCM72BA32•MCM72BA64
	3

	32K x 72 BurstRAM MEMORY MODULE BLOCK DIAGRAM
A15	NC
15	MCM67B518
A0 ± A14	A0 ± A14	LW	W0
			8
ADSP	ADSP	DQ0 ± DQ7	DQ0 ± DQ7
ADSC	ADSC	DQ8	DQP0
ADV	ADV	UW	W1
K0	K	DQ9 ± DQ16	8
			DQ8 ± DQ15
G0	G	DQ17	DQP1
E0	E
	MCM67B518
	A0 ± A14	LW	W2
			8
	ADSP	DQ0 ± DQ7	DQ16 ± DQ23
	ADSC	DQ8	DQP2
	ADV	UW	W3
			8
	K	DQ9 ± DQ16	DQ24 ± DQ31
	G	DQ17	DQP3
	E
	MCM67B518
	A0 ± A14	LW	W4
			8
	ADSP	DQ0 ± DQ7	DQ32 ± DQ39
	ADSC	DQ8	DQP4
	ADV	UW	W5
			8
K1	K	DQ9 ± DQ16	DQ40 ± DQ47
G1	G	DQ17	DQP5
E1	E
	MCM67B518
	A0 ± A14	LW	W6
			8
	ADSP	DQ0 ± DQ7	DQ48 ± DQ55
	ADSC	DQ8	DQP6
	ADV	UW	W7
	K	DQ9 ± DQ16	8
			DQ56 ± DQ63
	G	DQ17	DQP7
	E
MCM72BA32•MCM72BA64			MOTOROLA FAST SRAM
4

MCM67B618 BLOCK DIAGRAM (See Note)

	ADV	BURST LOGIC
				INTERNAL
K		Q0	A0′	ADDRESS
	BINARY COUNTER		A0	16	64K ×18
					MEMORY
		Q1	A1′		ARRAY
ADSC	CLR		A1
ADSP
	A1 ± A0		2
			A2 ± A15
A0 ± A15	ADDRESS
	REGISTER
					9	9
	16			18
UW	WRITE			DATA±IN
	REGISTER
LW				REGISTERS
E	ENABLE				OUTPUT
	REGISTER				BUFFER
G				9	9
	9
DQ0 ± DQ8

9

DQ9 ± DQ17

NOTE: All registers are positive±edge triggered. The ADSC or ADSP signals control the duration of the burst and the start of the next burst. When ADSP is sampled low, any ongoing burst is interrupted and a read (independent of W and ADSC) is performed using the new external address. Alternatively, an ADSP±initiated two cycle WRITE can be performed by asserting ADSP and a valid address on the first cycle, then negating both ADSP and ADSC and asserting LW and/or UW with valid data on the second cycle (see Single Write Cycle in WRITE CYCLES timing diagram).

When ADSC is sampled low (and ADSP is sampled high), any ongoing burst is interrupted and a read or write (dependent on W) is performed using the new external address. Chip enable (E) is sampled only when a new base address is loaded. After the first cycle of the burst, ADV controls subsequent burst cycles. When ADV is sampled low, the internal address is advanced prior to the operation. When ADV is sampled high, the internal address is not advanced, thus inserting a wait state into the burst sequence accesses. Upon completion of a burst, the address will wrap around to its initial state. See BURST SEQUENCE TABLE. Write refers to either or both byte write enables (LW, UW).

BURST SEQUENCE TABLE (See Note)

External Address	A15 ± A2	A1				A0
1st Burst Address	A15 ± A2	A1
						A0
2nd Burst Address	A15 ± A2					A0
			A1
3rd Burst Address	A15 ± A2
			A1			A0

NOTE: The burst wraps around to its initial state upon completion.

MOTOROLA FAST SRAM	MCM72BA32•MCM72BA64
	5