Motorola MCM6227BJ25R2, MCM6227BJ35, MCM6227BJ35R2, MCM6227BWJ15, MCM6227BJ17 Datasheet

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Order this document by MCM6227B/D

1M x 1 Bit Static Random

Access Memory

The MCM6227B is a 1,048,576 bit static random±access memory organized as 1,048,576 words of 1 bit. Static design eliminates the need for external clocks or timing strobes while CMOS circuitry reduces power consumption and provides for greater reliability.

The MCM6227B is each equipped with a chip enable (E) pin. This feature provides reduced system power requirements without degrading access time performance.

The MCM6227B is available in 300 mil and 400 mil, 28±lead surface±mount SOJ packages.

•Single 5 V ± 10% Power Supply

•Fast Access Times: 15/17/20/25/35 ns

•Equal Address and Chip Enable Access Times

•Input and Output are TTL Compatible

•Three±State Output

•Low Power Operation: 115/110/105/100/95 mA Maximum, Active AC

BLOCK DIAGRAM

A

A

	A
	A		MEMORY MATRIX
		ROW
	A		512 ROWS x
		DECODER
			2048 x 1 COLUMNS
	A
	A
	A
	A

D	INPUT	COLUMN I/O		Q
	DATA
	CONTROL	COLUMN DECODER
E
	A A A	A A A A A	A A	A
W

MCM6227B

J PACKAGE 300 MIL SOJ CASE 810B±03

WJ PACKAGE 400 MIL SOJ CASE 810±03

PIN ASSIGNMENT

	A			1	28		VCC
	A			2	27		A
	A			3	26			A
	A			4	25		A
	A			5	24			A
	A			6	23		A
NC				7	22		A
	A			8	21		NC*
	A			9	20		A
	A			10	19		A
	A			11	18		A
	Q			12	17			A
				13	16		D
W
VSS					15
				14			E

PIN NAMES

A . . . . . . . . . . . . . . . . . . . . Address Inputs

W . . . . . . . . . . . . . . . . . . . . . Write Enable

E . . . . . . . . . . . . . . . . . . . . . . Chip Enable

D . . . . . . . . . . . . . . . . . . . . . . . . Data Input

Q . . . . . . . . . . . . . . . . . . . . . Data Output

NC . . . . . . . . . . . . . . . . . . No Connection

VCC . . . . . . . . . . . . . + 5 V Power Supply

VSS . . . . . . . . . . . . . . . . . . . . . . . Ground

*If not used for no connect, then do not exceed voltages of ± 0.5 to VCC + 0.5 V.

This pin is used for manufacturing diagnostics.

REV 3 10/31/96

MOTOROLA FAST SRAM	MCM6227B
Motorola, Inc. 1994
	1

TRUTH TABLE

E	W	Mode	I/O Pin	Cycle	Current
H	X	Not Selected	High±Z	Ð	ISB1, ISB2
L	H	Read	Dout	Read	ICCA
L	L	Write	High±Z	Write	ICCA

H = High, L = Low, X = Don't Care

ABSOLUTE MAXIMUM RATINGS (See Note)

Rating	Symbol	Value	Unit
Power Supply Voltage Relative to VSS	VCC	± 0.5 to 7.0	V
Voltage Relative to VSS for Any Pin	Vin, Vout	± 0.5 to VCC + 0.5	V
Except VCC
Output Current	Iout	± 20	mA
Power Dissipation	PD	1.1	W
Temperature Under Bias	Tbias	± 10 to + 85	°C
Operating Temperature	TA	0 to + 70	°C
Storage Temperature	Tstg	± 55 to + 150	°C

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPER-

ATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.

This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to these high±impedance circuits.

This CMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow of at least 500 linear feet per minute is maintained.

DC OPERATING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 V ± 10%, TA = 0 to 70°C, Unless Otherwise Noted)

RECOMMENDED OPERATING CONDITIONS

Parameter	Symbol	Min	Max	Unit
Supply Voltage (Operating Voltage Range)	VCC	4.5	5.5	V
Input High Voltage	VIH	2.2	VCC +0.3**	V
Input Low Voltage	VIL	± 0.5*	0.8	V

*VIL (min) = ± 0.5 V dc; VIL (min) = ± 2.0 V ac (pulse width ≤ 20 ns).

**VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2 V ac (pulse width ≤ 20 ns).

DC CHARACTERISTICS AND SUPPLY CURRENTS

		Parameter	Symbol	Min	Max	Unit
Input Leakage Current (All Inputs, Vin = 0 to VCC)			Ilkg(I)	Ð	± 1	μA
Output Leakage Current (E = VIH, Vout = 0 to VCC)			Ilkg(O)	Ð	± 1	μA
AC Active Supply Current (Iout = 0 mA, VCC = max)			ICCA			mA
		MCM6227B±15: tAVAV = 15 ns		Ð	115
		MCM6227B±17: tAVAV = 17 ns		Ð	110
		MCM6227B±20: tAVAV = 20 ns		Ð	105
		MCM6227B±25: tAVAV = 25 ns		Ð	100
		MCM6227B±35: tAVAV = 35 ns		Ð	95
AC Standby Current (VCC = max, E = VIH, f ≤ fmax)			ISB1			mA
		MCM6227B±15: tAVAV = 15 ns		Ð	40
		MCM6227B±17: tAVAV = 17 ns		Ð	35
		MCM6227B±20: tAVAV = 20 ns		Ð	30
		MCM6227B±25: tAVAV = 25 ns		Ð	25
		MCM6227B±35: tAVAV = 35 ns		Ð	20
CMOS Standby Current (E ≥ VCC ± 0.2 V, Vin ≤ VSS + 0.2 V			ISB2	Ð	5	mA
or ≥ VCC ± 0.2 V, VCC = max, f = 0 MHz)
Output Low Voltage (IOL = + 8.0 mA)			VOL	Ð	0.4	V
Output High Voltage (IOH = ± 4.0 mA)			VOH	2.4	Ð	V

MCM6227B	MOTOROLA FAST SRAM
2

CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested)

	Characteristic			Symbol	Typ	Max	Unit
Input Capacitance	All Inputs Except Clocks and D,	Q		Cin	4	6	pF
	E and W				5	8
Input and Output Capacitance	D, Q			Cin, Cout	5	8	pF

AC OPERATING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted)

Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	0 to 3.0	V	Output Timing Measurement Reference Level . . . . . .	. . . . . . . 1.5 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 2 ns		Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	See Figure 1a
Input Timing Measurement Reference Level . . . . . . . . . . . .	. . . 1.5	V

READ CYCLE TIMING (See Notes 1 and 2)

6227B±15

6227B±17

6227B±20

6227B±25

6227B±35

Parameter

Symbol

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Unit

Notes

Read Cycle Time

tAVAV

15

Ð

17

Ð

20

Ð

25

Ð

35

Ð

ns

2, 3

Address Access Time

tAVQV

Ð

15

Ð

17

Ð

20

Ð

25

Ð

35

ns

Enable Access Time

tELQV

Ð

15

Ð

17

Ð

20

Ð

25

Ð

35

ns

4

Output Hold from

tAXQX

5

Ð

5

Ð

5

Ð

5

Ð

5

Ð

ns

Address Change

Enable Low to Output

tELQX

5

Ð

5

Ð

5

Ð

5

Ð

5

Ð

ns

5, 6, 7

Active

Enable High to Output

tEHQZ

Ð

6

Ð

7

Ð

7

Ð

8

Ð

8

ns

5, 6, 7

High±Z

NOTES:

1.W is high for read cycle.

2.Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles.

3.All timings are referenced from the last valid address to the first transitioning address.

4.Addresses valid prior to or coincident with E going low.

5.At any given voltage and temperature, tEHQZ max is less than tELQX min, both for a given device and from device to device.

6.Transition is measured ± 500 mV from steady±state voltage with load of Figure 1b.

7.This parameter is sampled and not 100% tested.

8.Device is continuously selected (E ≤ VIL).

			+ 5 V
OUTPUT	RL = 50 Ω		480 Ω
	OUTPUT
Z0	= 50 Ω	Ω	5 pF
	255
	VL = 1.5 V
(a)			(b)

TIMING LIMITS

The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the system must supply at least that much time. On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never provides data later than that time.

Figure 1. AC Test Loads

MOTOROLA FAST SRAM	MCM6227B
	3