Motorola MCM67M618AFN10, MCM67M618AFN12, MCM67M618AFN9, MCM67M618FN9, MCM67M618FN10 Datasheet

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Order this document by MCM67M618A/D

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64K x 18 Bit BurstRAM

Synchronous Fast Static RAM

With Burst Counter and Self±Timed Write

The MCM67M618A is a 1,179,648 bit synchronous static random access memory designed to provide a burstable, high±performance, secondary cache for the MC68040 and PowerPC microprocessors. It is organized as 65,536 words of 18 bits, fabricated using Motorola's high±performance silicon±gate BiCMOS technology. The device integrates input registers, a 2±bit counter, high speed SRAM, and high drive capability outputs onto a single monolithic circuit for reduced parts count implementation of cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K). BiCMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability.

Addresses (A0 ± A15), data inputs (DQ0 ± DQ17), and all control signals, except output enable (G), are clock (K) controlled through positive±edge± triggered noninverting registers.

Bursts can be initiated with either transfer start processor (TSP) or transfer

start cache controller (TSC) input pins. Subsequent burst addresses are generated internally by the MCM67M618A (burst sequence imitates that of the MC68040) and controlled by the burst address advance (BAA) input pin. The following pages provide more detailed information on burst controls.

Write cycles are internally self±timed and are initiated by the rising edge of the clock (K) input. This feature eliminates complex off±chip write pulse generation and provides increased flexibility for incoming signals.

Dual write enables (LW and UW) are provided to allow individually writeable

bytes. LW controls DQ0 ± DQ8 (the lower bits), while UW controls DQ9 ± DQ17 (the upper bits).

This device is ideally suited for systems that require wide data bus widths and cache memory.

•Single 5 V ± 5% Power Supply

•Fast Access Times: 9/10/12 ns Max

•Byte Writeable via Dual Write Strobes

•Internal Input Registers (Address, Data, Control)

•Internally Self±Timed Write Cycle

•TSP, TSC, and BAA Burst Control Pins

•Asynchronous Output Enable Controlled Three±State Outputs

•Common Data Inputs and Data Outputs

•High Board Density 52±PLCC Package

•3.3 V I/O Compatible

MCM67M618A

FN PACKAGE

PLASTIC

CASE 778±02

PIN ASSIGNMENT

	A6	A7		E		UW		LW	TSC		TSP		BAA	K		G A8	A9	A10
	7	6	5		4		3		2	1		52		51 50 49 48 47
DQ9	8																	46	DQ8
DQ10	9																	45	DQ7
VCC	10																	44	DQ6
VSS	11																	43	V
DQ11	12																	42	CC
																			VSS
DQ12	13																	41	DQ5
DQ13	14																	40	DQ4
DQ14	15																	39	DQ3
VSS	16																	38	DQ2
VCC	17																	37	V
DQ15																			SS
	18																	36	VCC
DQ16	19																	35	DQ1
DQ17	20																	34	DQ0
	21	22 23 24					25 26 27 28 29 30 31 32 33
	A5	A4		A3		A2		A1	A0		V		V	A15		A14 A13	A12	A11
											SS		CC

PIN NAMES

A0 ± A15 . . . . . . . . . . . . . . . . Address Inputs

K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock

BAA . . . . . . . . . . . . Burst Address Advance

LW . . . . . . . . . . . . Lower Byte Write Enable

UW . . . . . . . . . . . . Upper Byte Write Enable

TSP, TSC . . . . . . . . . . . . . . . . Transfer Start

E . . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable

G . . . . . . . . . . . . . . . . . . . . . . Output Enable

DQ0 ± DQ17 . . . . . . . . . . Data Input/Output

VCC . . . . . . . . . . . . . . . . + 5 V Power Supply

VSS . . . . . . . . . . . . . . . . . . . . . . . . . . Ground

All power supply and ground pins must be connected for proper operation of the device.

BurstRAM is a trademark of Motorola, Inc.

PowerPC is a trademark of IBM Corp.

This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice.

REV 1 5/95

Motorola, Inc. 1994

BLOCK DIAGRAM (See Note)

BURST LOGIC

					INTERNAL
BAA				A1′	ADDRESS
K			Q1
		BINARY			16
							64K x 18
		COUNTER					MEMORY
			Q0	A0′			ARRAY
TSC	LOAD
TSP		D1	D0
	A1	A0
EXTERNAL
ADDRESS	ADDRESS			A15 ± A2
A15 ± A0	REGISTERS					18	9	9
	16
	WRITE					DATA±IN
UW	REGISTER
LW						REGISTERS
E	ENABLE						OUTPUT
	REGISTER						BUFFER
					9	9
G
9
DQ0 ± DQ8

9

DQ9 ± DQ17

NOTE: All registers are positive±edge triggered. The TSC or TSP signals control the duration of the burst and the start of the next burst. When TSP is sampled low, any ongoing burst is interrupted and a read (independent of W and TSC) is performed using the new external address. Alternatively, a TSP±initiated two cycle WRITE can be performed by asserting TSP and a valid address on the first cycle, then negating both TSP and TSC and asserting LW and/or UW with valid data on the second cycle (see Single Write Cycle in WRITE CYCLES timing diagram).

When TSC is sampled low (and TSP is sampled high), any ongoing burst is interrupted and a read or write (dependent on W) is performed using the new external address. Chip enable (E) is sampled only when a new base address is loaded. After the first cycle of the burst, BAA controls subsequent burst cycles. When BAA is sampled low, the internal address is advanced prior to the operation. When BAA is sampled high, the internal address is not advanced, thus inserting a wait state into the burst sequence accesses. Upon completion of a burst, the address will wrap around to its initial state. See BURST SEQUENCE TABLE. Write refers to either or both byte write enables (LW, UW).

BURST SEQUENCE GRAPH (See Note)

0,0

A1′, A0′= 1,1

0,1

1,0

NOTE: The external two values for A1 and A0 provide the starting point for the burst sequence graph. The burst logic advances A1 and A0 as shown above.

MCM67M618A	MOTOROLA FAST SRAM
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SYNCHRONOUS TRUTH TABLE (See Notes 1, 2, and 3)

E

TSP

TSC

BAA

LW or UW

K

Address

Operation

H

L

X

X

X

L±H

N/A

Deselected

H

X

L

X

X

L±H

N/A

Deselected

L

L

X

X

X

L±H

External Address

Read Cycle, Begin Burst

L

H

L

X

L

L±H

External Address

Write Cycle, Begin Burst

L

H

L

X

H

L±H

External Address

Read Cycle, Begin Burst

X

H

H

L

L

L±H

Next Address

Write Cycle, Continue Burst

X

H

H

L

H

L±H

Next Address

Read Cycle, Continue Burst

X

H

H

H

L

L±H

Current Address

Write Cycle, Suspend Burst

X

H

H

H

H

L±H

Current Address

Read Cycle, Suspend Burst

NOTES:

1.X means Don't Care.

2.All inputs except G must meet setup and hold times for the low±to±high transition of clock (K).

3.Wait states are inserted by suspending burst.

ASYNCHRONOUS TRUTH TABLE (See Notes 1 and 2)

Operation
		G		I/O Status
Read		L		Data Out
Read		H		High±Z
Write		X		High±Z Ð Data In
Deselected		X		High±Z

NOTES:

1.X means Don't Care.

2.For a write operation following a read operation, G must be high before the input data required setup time and held high through the input data hold time.

ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS = 0 V)

Rating	Symbol	Value		Unit
Power Supply Voltage	VCC	± 0.5 to +	7.0	V
Voltage Relative to VSS for Any	Vin, Vout	± 0.5 to VCC + 0.5		V
Pin Except VCC
Output Current (per I/O)	Iout	± 30		mA
Power Dissipation	PD	1.6		W
Temperature Under Bias	Tbias	± 10 to +	85	°C
Operating Temperature	TA	0 to +70		°C
Storage Temperature	Tstg	± 55 to + 125		°C

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.

This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high±impedance circuit.

This BiCMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established.

This device contains circuitry that will ensure the output devices are in High±Z at power up.

MOTOROLA FAST SRAM	MCM67M618A
	3

DC OPERATING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 V ± 5%, TA = 0 to + 70°C, Unless Otherwise Noted)

RECOMMENDED OPERATING CONDITIONS (Voltages referenced to VSS = 0 V)

Parameter	Symbol	Min	Max	Unit
Supply Voltage (Operating Voltage Range)	VCC	4.75	5.25	V
Input High Voltage	VIH	2.2	VCC + 0.3**	V
Input Low Voltage	VIL	± 0.5*	0.8	V

*VIL (min) = ± 0.5 V dc; VIL (min) = ± 2.0 V ac (pulse width ≤ 20.0 ns) for I ≤ 20.0 mA.

**VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width ≤ 20.0 ns) for I ≤ 20.0 mA.

DC CHARACTERISTICS AND SUPPLY CURRENTS

Parameter

Symbol

Min

Max

Unit

Input Leakage Current (All Inputs, Vin = 0 to VCC)

Ilkg(I)

Ð

± 1.0

μA

= VIH)

Ilkg(O)

± 1.0

μA

Output Leakage Current (G

Ð

ICCA9

AC Supply Current (G

= VIH, E = VIL, Iout = 0 mA, All Inputs = VIL or VIH,

Ð

275

mA

VIL = 0.0 V and VIH ≥ 3.0 V, Cycle Time ≥ tKHKH min)

ICCA10

265

ICCA12

250

= VIH, Iout = 0 mA, All Inputs = VIL and VIH,

ISB1

Ð

95

mA

AC Standby Current (E

VIL = 0.0 V and VIH ≥ 3.0 V, Cycle Time ≥ tKHKH min)

Output Low Voltage (IOL = + 8.0 mA)

VOL

Ð

0.4

V

Output High Voltage (IOH = ± 4.0 mA)

VOH

2.4

3.3

V

NOTE: Good decoupling of the local power supply should always be used. DC characteristics are guaranteed for all possible 68040 and PowerPC bus cycles.

CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested)

Parameter	Symbol	Min	Typ	Max	Unit
Input Capacitance (All Pins Except DQ0 ± DQ17)	Cin	Ð	4	5	pF
Input/Output Capacitance (DQ0 ± DQ17)	CI/O	Ð	6	8	pF

MCM67M618A	MOTOROLA FAST SRAM
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