Motorola MCM62449WJ35R2, MCM62449WJ25R2, MCM62449WJ20, MCM62449WJ20R2, MCM62449WJ25 Datasheet

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Order this document by MCM6249/D

1M x 4 Bit Static Random

Access Memory

The MCM6249 is a 4,194,304 bit static random access memory organized as 1,048,576 words of 4 bits, fabricated using high±performance silicon±gate CMOS technology. Static design eliminates the need for external clocks or timing strobes, while CMOS circuitry reduces power consumption and provides for greater reliability.

The MCM6249 is equipped with chip enable (E) and output enable (G) pins, allowing for greater system flexibility and eliminating bus contention problems. Either input, when high, will force the outputs into high impedance.

The MCM6249 is available in a 400 mil, 32±lead surface±mount SOJ package.

•Single 5 V ± 10% Power Supply

•Fast Access Time: 20/25/35 ns

•Equal Address and Chip Enable Access Time

•All Inputs and Outputs are TTL Compatible

•Three±State Outputs

•Power Operation: 190/175/160 mA Maximum, Active AC

			BLOCK DIAGRAM
	A13
	A12
	A11
	A10
	A9	ROW		MEMORY MATRIX
				1024 ROWS x
	A8	DECODER
				4096 COLUMNS
	A7
	A6
	A5
	A4

DQ0				COLUMN I/O
INPUT			COLUMN DECODER
DATA
CONTROL
DQ3
A18	A17	A16	A15	A14	A19	A3	A2	A1	A0
									DQ0
E
W									DQ3
G
REV 4
5/95

MCM6249

WJ PACKAGE 400 MIL SOJ CASE 857A±02

PIN ASSIGNMENT

A7				1	32	A1
A8				2	31	A0
A9				3	30	A5
A17				4	29	A4
A6				5	28	A19
		E		6	27	G
DQ0				7	26	DQ3
VCC				8	25	VSS
V				9	24	VCC
SS
DQ1				10	23	DQ2
	W			11	22	A2
A13				12	21	A16
A18				13	20	A15
A10				14	19	A14
A11				15	18	A3
A12				16	17	NC

PIN NAMES

A0 ± A19 . . . . . . . . . . . . Address Inputs

W . . . . . . . . . . . . . . . . . . . . Write Enable

G . . . . . . . . . . . . . . . . . . . Output Enable

E . . . . . . . . . . . . . . . . . . . . . . Chip Enable

DQ0 ± DQ3 . . . . . . . . Data Input/Output

NC . . . . . . . . . . . . . . . . . No Connection

VCC . . . . . . . . . . . . + 5 V Power Supply

VSS . . . . . . . . . . . . . . . . . . . . . . . Ground

MOTOROLAMotorola, Inc. 1995FAST SRAM

1

TRUTH TABLE (X = Don't Care)

E	G	W	Mode	I/O Pin	Cycle	Current
H	X	X	Not Selected	High±Z	Ð	ISB1, ISB2
L	H	H	Output Disabled	High±Z	Ð	ICCA
L	L	H	Read	Dout	Read	ICCA
L	X	L	Write	High±Z	Write	ICCA

ABSOLUTE MAXIMUM RATINGS (See Note)

Rating	Symbol	Value		Unit
Power Supply Voltage Relative to VSS	VCC	± 0.5 to +	7.0	V
Voltage Relative to VSS for Any Pin	Vin, Vout	± 0.5 to VCC + 0.5		V
Except VCC
Output Current (per I/O)	Iout	± 20		mA
Power Dissipation	PD	1.0		W
Temperature Under Bias	Tbias	± 10 to +	85	°C
Operating Temperature	TA	0 to + 70		°C
Storage Temperature Ð Plastic	Tstg	± 55 to + 150		°C

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.

This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to these high impedance circuits.

This CMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow of at least 500 linear feet per minute is maintained.

DC OPERATING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted)

RECOMMENDED OPERATING CONDITIONS

		Parameter		Symbol	Min	Typ	Max	Unit
Supply Voltage (Operating Voltage Range)				VCC	4.5	5.0	5.5	V
Input High Voltage				VIH	2.2	Ð	VCC + 0.3	V
Input Low Voltage				VIL	± 0.5*	Ð	0.8	V
* VIL (min) = ± 0.5 V dc; VIL (min) = ± 2.0 V ac (pulse width ≤ 2.0 ns).
DC CHARACTERISTICS
		Parameter			Symbol	Min	Max	Unit
Input Leakage Current (All Inputs, Vin = 0 to VCC)					Ilkg(I)	Ð	± 1.0	μA
Output Leakage Current (E = VIH, Vout = 0 to VCC)					Ilkg(O)	Ð	± 1.0	μA
Output Low Voltage (IOL = + 8.0 mA)					VOL	Ð	0.4	V
Output High Voltage (IOH = ± 4.0 mA)					VOH	2.4	Ð	V
POWER SUPPLY CURRENTS
		Parameter		Symbol	Min	Typ	Max	Unit
AC Active Supply Current (Iout = 0 mA,			MCM6249±20: tAVAV = 20 ns	ICC	Ð	175	190	mA
VCC = max)			MCM6249±25: tAVAV = 25 ns		Ð	160	175
			MCM6249±35: tAVAV = 35 ns		Ð	145	160
AC Standby Current (VCC = max,			MCM6249±20: tAVAV = 20 ns	ISB1	Ð	50	60	mA
E = VIH, No other restrictions on			MCM6249±25: tAVAV = 25 ns		Ð	40	50
other inputs)			MCM6249±35: tAVAV = 35 ns		Ð	35	40
CMOS Standby Current (E ≥ VCC ± 0.2 V, Vin ≤ VSS + 0.2 V or				ISB2	Ð	10	15	mA
≥ VCC ± 0.2 V) (VCC = max, f = 0 MHz)

MCM6249	MOTOROLA FAST SRAM
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CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested)

	Parameter			Symbol	Typ	Max	Unit
Input Capacitance	All Inputs Except Clocks and	DQs		Cin	4	6	pF
	E, G, W			Cck	5	8
Input/Output Capacitance		DQ		CI/O	5	8	pF

AC OPERATING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted)

Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	0 to 3.0	V	Output Timing Measurement Reference Level . . . . . .	. . . . . . . 1.5 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 2 ns		Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	See Figure 1a
Input Timing Measurement Reference Level . . . . . . . . . . . .	. . . 1.5	V

READ CYCLE TIMING (See Note 1)

		MCM6249±20		MCM6249±25		MCM6249±35
Parameter	Symbol	Min	Max	Min	Max	Min	Max	Unit	Notes
Read Cycle Time	tAVAV	20	Ð	25	Ð	35	Ð	ns	2, 3
Address Access Time	tAVQV	Ð	20	Ð	25	Ð	35	ns
Enable Access Time	tELQV	Ð	20	Ð	25	Ð	35	ns	4
Output Enable Access Time	tGLQV	Ð	6	Ð	8	Ð	10	ns
Output Hold from Address Change	tAXQX	5	Ð	5	Ð	5	Ð	ns
Enable Low to Output Active	tELQX	5	Ð	5	Ð	5	Ð	ns	5, 6, 7
Output Enable Low to Output Active	tGLQX	0	Ð	0	Ð	0	Ð	ns	5, 6, 7
Enable High to Output High±Z	tEHQZ	0	9	0	10	0	12	ns	5, 6, 7
Output Enable High to Output High±Z	tGHQZ	0	9	0	10	0	12	ns	5, 6, 7
Power Up Time	tELICCH	0	Ð	0	Ð	0	Ð	ns
Power Down Time	tEHICCL	Ð	20	Ð	25	Ð	35	ns
NOTES:

1.W is high for read cycle.

2.Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus con± tention conditions during read and write cycles.

3.All read cycle timings are referenced from the last valid address to the first transitioning address.

4.Addresses valid prior to or coincident with E going low/E going high.

5.At any given voltage and temperature, tEHQZ max t tELQX min, and tGHQZ max t tGLQX min, both for a given device and from device to device.

6.Transition is measured ± 500 mV from steady±state voltage with load of Figure 1b.

7.This parameter is sampled and not 100% tested.

8.Device is continuously selected (E ≤ VIL, G ≤ VIL).

			+ 5 V
OUTPUT	RL = 50 Ω		480 Ω
	OUTPUT
Z0	= 50 Ω	Ω
	255		5 pF
	VL = 1.5 V
	(a)		(b)

TIMING LIMITS

The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the system must supply at least that much time. On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never provides data later than that time.

Figure 1. AC Test Loads

MOTOROLA FAST SRAM	MCM6249
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