Motorola MCM6343YJ12R, MCM6343YJ15, MCM6343YJ15R, MCM6343TS15, MCM6343YJ12 Datasheet

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Motorola MCM6343YJ12R, MCM6343YJ15, MCM6343YJ15R, MCM6343TS15, MCM6343YJ12 Datasheet

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Order this document by MCM6343/D

Product Preview

256K x 16 Bit 3.3 V Asynchronous

Fast Static RAM

The MCM6343 is a 4,194,304±bit static random access memory organized as 262,144 words of 16 bits. Static design eliminates the need for external clocks or timing strobes.

The MCM6343 is equipped with chip enable (E), write enable (W), and output enable (G) pins, allowing for greater system flexibility and eliminating bus contention problems. Separate byte enable controls (LB and UB) allow individual bytes to be written and read. LB controls the lower bits DQ0 to DQ7, while UB controls the upper bits DQ8 to DQ15.

The MCM6343 is available in a 400 mil, 44±lead small±outline SOJ package and a 44±lead TSOP Type II package.

Single 3.3 V ± 0.3 V Power Supply

Fast Access Time: 12/15 ns

Equal Address and Chip Enable Access Time

All Inputs and Outputs are TTL Compatible

Data Byte Control

Fully Static Operation

Power Operation: 250/240/230 mA Maximum, Active AC

Commercial and Standard Industrial Temperature Option: ± 40 to + 85°C

 

BLOCK DIAGRAM

G OUTPUT

HIGH BYTE OUTPUT ENABLE

ENABLE

 

BUFFER

LOW BYTE OUTPUT ENABLE

 

 

 

9

 

 

8

HIGH

8

A

ADDRESS

 

 

 

BYTE

 

 

 

 

 

 

 

 

 

 

18

BUFFERS

9

ROW

COLUMN

 

OUTPUT

 

 

 

DECODER

DECODER

 

BUFFER

 

 

 

 

 

 

 

8

HIGH

8

E

CHIP

 

 

 

 

BYTE

 

 

 

 

 

WRITE

 

 

ENABLE

 

 

 

 

 

 

 

 

 

 

 

 

DRIVER

 

 

BUFFER

 

 

 

 

 

 

 

 

 

 

 

SENSE

 

 

 

 

 

256K x 16

16

 

 

 

 

 

AMPS

 

 

 

 

 

BIT

 

 

 

WRITE

 

 

 

LOW

 

W

 

MEMORY

 

8

8

 

ENABLE

 

ARRAY

 

BYTE

 

 

 

 

 

 

BUFFER

 

 

 

 

 

OUTPUT

 

 

 

 

 

 

 

 

BUFFER

 

 

 

 

 

 

 

8

LOW

8

 

 

 

 

 

 

BYTE

LB

BYTE

 

 

 

 

 

WRITE

 

 

 

 

 

 

 

DRIVER

 

UB

ENABLE

 

 

HIGH BYTE WRITE ENABLE

 

 

 

 

 

 

BUFFER

 

 

 

 

 

 

 

LOW BYTE WRITE ENABLE

MCM6343

YJ PACKAGE 400 MIL SOJ CASE 919±01

TS PACKAGE

TSOP TYPE II

CASE 924A±02

PIN ASSIGNMENT

 

A

 

1

44

 

A

 

 

 

 

A

 

2

43

 

A

 

 

 

A

 

3

42

 

A

 

 

 

 

 

 

 

 

 

 

 

 

 

A

 

4

41

 

G

 

 

 

A

 

5

40

 

 

 

 

 

 

 

 

 

 

UB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

E

 

6

39

 

LB

 

 

DQ0

 

7

38

 

DQ15

 

 

DQ1

 

8

37

 

DQ14

 

 

DQ2

 

9

36

 

DQ13

 

 

DQ3

 

10

35

 

DQ12

 

 

VDD

 

11

34

 

VSS

 

 

 

 

VSS

 

12

33

 

 

VDD

 

 

 

DQ4

 

13

32

 

 

DQ11

 

 

 

DQ5

 

14

31

 

 

DQ10

 

 

 

 

 

 

DQ6

 

15

30

 

 

DQ9

 

 

 

 

 

 

DQ7

 

16

29

 

 

DQ8

 

 

 

 

 

 

W

 

17

28

 

 

NC

 

 

 

A

 

18

27

 

 

A

 

 

 

A

 

19

26

 

 

A

 

 

 

A

 

20

25

 

 

A

 

 

 

A

 

21

24

 

 

A

 

 

 

A

 

22

23

 

 

A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PIN NAMES

A0 ± A17 . . . . . . . . . . . . . . . . . Address Input

E . . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable

W . . . . . . . . . . . . . . . . . . . . . . . Write Enable

G . . . . . . . . . . . . . . . . . . . . . . Output Enable

UB . . . . . . . . . . . . . . . . . . . . . . . . Upper Byte

LB . . . . . . . . . . . . . . . . . . . . . . . . . Lower Byte

DQ0 ± DQ15 . . . . . . . . . . Data Input/Output

VDD . . . . . . . . . . . . . . + 3.3 V Power Supply

VSS . . . . . . . . . . . . . . . . . . . . . . . . . . Ground

NC . . . . . . . . . . . . . . . . . . . . . No Connection

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.

REV 2 2/10/98

Motorola, Inc. 1998

MCM6343

MOTOROLA FAST SRAM

 

1

TRUTH TABLE (X = Don't Care)

E

G

W

LB

UB

Mode

VDD Current

DQ0 ± DQ7

DQ8 ± DQ15

H

X

X

X

X

Not Selected

ISB1, ISB2

High±Z

High±Z

L

H

H

X

X

Output Disabled

IDDA

High±Z

High±Z

L

X

X

H

H

Output Disabled

IDDA

High±Z

High±Z

L

L

H

L

H

Low Byte Read

IDDA

Dout

High±Z

L

L

H

H

L

High Byte Read

IDDA

High±Z

Dout

L

L

H

L

L

Word Read

IDDA

Dout

Dout

L

X

L

L

H

Low Byte Write

IDDA

Din

High±Z

L

X

L

H

L

High Byte Write

IDDA

High±Z

Din

L

X

L

L

L

Word Write

IDDA

Din

Din

ABSOLUTE MAXIMUM RATINGS (See Notes)

Rating

 

Symbol

Value

 

Unit

 

 

 

 

 

 

Supply Voltage

 

VDD

± 0.5 to +

4.6

V

Voltage on Any Pin

 

Vin

± 0.5 to VDD + 0.5

V

Output Current per Pin

 

Iout

± 20

 

mA

Package Power Dissipation

 

PD

TBD

 

W

Temperature Under Bias

Commercial

Tbias

± 10 to +

85

°C

 

Industrial

 

± 45 to +

90

 

 

 

 

 

 

Operating Temperature

Commercial

TA

0 to + 70

°C

 

Industrial

 

± 45 to +

85

 

 

 

 

 

 

Storage Temperature

 

Tstg

± 55 to + 150

°C

NOTES:

 

 

 

 

 

1.Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.

2.All voltages are referenced to VSS.

3.Power dissipation capability will be dependent upon package characteristics and use environment.

This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to these high±impedance circuits.

This CMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow of at least 500 linear feet per minute is maintained.

MCM6343

MOTOROLA FAST SRAM

2

 

DC OPERATING CONDITIONS AND CHARACTERISTICS

(VDD = 3.3 V ± 0.3 V, TA = 0 to 70°C, Unless Otherwise Noted) (TA = ± 40 to + 85°C for Industrial Temperature Offering)

RECOMMENDED OPERATING CONDITIONS

Parameter

Symbol

Min

Typ

Max

Unit

 

 

 

 

 

 

Power Supply Voltage

VDD

3.0

3.3

3.6

V

Input High Voltage

VIH

2.2

Ð

VDD + 0.3**

V

Input Low Voltage

VIL

± 0.5*

Ð

0.8

V

*VIL (min) = ± 0.5 V dc; VIL (min) = ± 2.0 V ac (pulse width 20 ns) for I 20.0 mA.

**VIH (max) = VDD + 0.3 V dc; VIH (max) = VDD + 2.0 V ac (pulse width 20 ns) for I 20.0 mA.

DC CHARACTERISTICS

 

 

Parameter

 

Symbol

Min

Max

Unit

 

 

 

 

 

 

 

 

Input Leakage Current (All Inputs, Vin = 0 to VDD)

 

Ilkg(I)

Ð

± 1.0

μA

Output Leakage Current (E = VIH, Vout = 0 to VDD)

 

Ilkg(O)

Ð

± 1.0

μA

Output Low Voltage

(IOL = + 4.0 mA)

VOL

Ð

0.4

V

 

 

 

(IOL = + 100 μA)

 

 

VSS + 0.2

 

Output High Voltage

(IOH = ± 4.0 mA)

VOH

2.4

Ð

V

 

 

 

(IOH = ± 100 μA)

 

VDD ± 0.2

 

 

POWER SUPPLY CURRENTS

 

 

 

 

 

± 40 to

 

Parameter

 

Symbol

 

0 to 70°C

+ 85°C

Unit

 

 

 

 

 

 

 

AC Active Supply Current

MCM6343±12: tAVAV = 12 ns

ICC

 

240

240

mA

(Iout = 0 mA, VCC = max)

MCM6343±15: tAVAV = 15 ns

 

 

230

 

 

AC Standby Current (VCC = max, E = VIH,

MCM6343±12: tAVAV = 12 ns

ISB1

 

50

55

mA

No other restrictions on other inputs)

MCM6343±15: tAVAV = 15 ns

 

 

45

50

 

CMOS Standby Current (E VCC ± 0.2 V, Vin VSS + 0.2 V or VCC ± 0.2 V)

ISB2

 

5

5

mA

(VCC = max, f = 0 MHz)

 

 

 

 

 

 

CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested)

 

 

 

 

 

 

 

 

 

Parameter

 

Symbol

 

Typ

Max

Unit

 

 

 

 

 

 

 

Address Input Capacitance

 

Cin

 

Ð

6

pF

Control Input Capacitance

 

Cin

 

Ð

6

pF

Input/Output Capacitance

 

CI/O

 

Ð

8

pF

MOTOROLA FAST SRAM

MCM6343

 

3

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