Motorola MCM69Q536TQ8, MCM69Q536TQ8R, MCM69Q536TQ6R, MCM69Q536TQ10, MCM69Q536TQ10R Datasheet

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Order this document by MCM69Q536/D

Advance Information

32K x 36 Bit Synchronous

Separate I/O SRAM

The Motorola MCM69Q536 is a 1 Megabit static random access memory, organized as 32K words of 36 bits. It features separate data input and data output buffers and incorporates input and output registers on board with high speed SRAM.

The MCM69Q536 allows the user to perform transparent writes and data pass through. Two data bus ports are provided Ð a data input (D) and a data output (Q) port.

The synchronous design allows for precise cycle control with the use of an external single clock (K). Address port, data input (D0 ± D35), data output (Q0 ± Q35), write enable (W), chip enables (E1, E2), and pass±through enable (PT) are registered on the rising edge of clock (K).

Any given cycle operates on only one address. However, for any cycle, reads and writes can be intermixed. Thus, one can perform a read, a write, or a combination read/ write during any one cycle. For a combination read/write, the contents of the array are read before the new data is written.

By using the pass±through function, the output port Q can be made to reflect either the contents of the array or the data presented to the input port D. For read/write or a read cycle with G low, the Q port will output the contents of the array. However, if PT is asserted, the Q port will instead output the data presented at the D input port.

• Single 3.3 V ± 5% Power Supply

•Fast Access Times: 6/8/10 ns Max

•Sustained Throughput of 2.98 Gigabits/Second

•Single Clock Operation

•Address, Data Input, E1, E2, PT, W, and Data Output Registers on Chip

•83 MHz Maximum Clock Cycle Time

•Self Timed Write

•Separate Data Input and Data Output Pins

•Pass±Through Feature

•Asynchronous Output Enable (G)

•LVTTL Compatible I/O

•No Dead Cycles Required for Reads after Writes or for Writes after Reads

•176 Pin TQFP Package

•Simultaneous Reads and Writes

MCM69Q536

TQ PACKAGE

176 LEAD TQFP

CASE 1101±01

Suggested Applications
Ð ATM	Ð Ethernet Switches		Ð Routers
Ð Cell/Frame Buffers	Ð SNA Switches		Ð Shared Memory
Product Family Configurations
Part	Dual	Single		Dual	Separate
Number	Address	Address		I/O	I/O
MCM69D536	n	Note 1		n	Note 2
MCM69D618	n	Note 1		n	Note 2
MCM69Q536
MCM69Q618
MCM67Q709
MCM67Q909
NOTES:

1.Tie AX and AY address ports together for the part to function as a single address part.

2.Tie GX high for DQX to be inputs and tie WY high and GY low for DQY to be outputs.

This document contains information on a new product. Specifications and information herein are subject to change without notice.

REV 3 11/20/97

MOTOROLA FAST SRAM	MCM69Q536
Motorola, Inc. 1997
	1

BLOCK DIAGRAM

K
15	ADDRESS	32K x 36 ARRAY
A0 ± A14	REGISTER

	W		WRITE	WRITE	SENSE
				DRIVER	AMP
		REGISTER
	PT		PT	PASS±THROUGH
		REGISTER
				DATA INPUT	DATA OUTPUT
				REGISTER	REGISTER
	E1	ENABLE	ENABLE
	E2	REGISTER 1	REGISTER 2
	G			D0 ± D35	Q0 ± Q35

MCM69Q536	MOTOROLA FAST SRAM
2

PIN ASSIGNMENT

			SS		Q19 D19				SS		DD		Q18 D18				A6 NC				A7 NC				SS		NC NC				NC		NC NC NC NC NC												DD SS				NC			G E2				E1		NC		W		NC			PT A8 NC						A9 NC				NC NC				D17 Q17				DD		SS		D16		Q16		SS
			V						V		V														V																		K V V																																								V		V						V
VSS		176			175		174	173			172		171		170	169		168		167		166			165		164	163		162			161	160		159		158		157			156	155			154		153		152			151		150		149	148			147		146			145		144		143	142			141		140	139			138	137			136		135	134			133
		1																																																																																									132
D20		2																																																																																									131
Q20		3																																																																																									130
VDD		4																																																																																									129
VSS		5																																																																																									128
D21		6																																																																																									127
Q21		7																																																																																									126
																																																																																											125
D22		8
Q22		9																																																																																									124
VDD		10																																																																																									123
VSS		11																																																																																									122
																																																																																											121
D23		12
																																																																																											120
Q23		13
																																																																																											119
D24		14
Q24		15																																																																																									118
																																																																																											117
VDD		16
VSS		17																																																																																									116
D25		18																																																																																									115
																																																																																											114
Q25		19
D26		20																																																																																									113
Q26		21																																																																																									112
VDD		22																																																																																									111
VSS		23																																																																																									110
Q27		24																																																																																									109
D27		25																																																																																									108
Q28		26																																																																																									107
D28		27																																																																																									106
VDD		28																																																																																									105
VSS		29																																																																																									104
Q29		30																																																																																									103
		31																																																																																									102
D29
Q30		32																																																																																									101
D30		33																																																																																									100
VDD		34																																																																																									99
																																																																																											98
VSS		35
Q31		36																																																																																									97
D31		37																																																																																									96
Q32		38																																																																																									95
D32		39																																																																																									94
VDD		40																																																																																									93
																																																																																											92
VSS		41
Q33		42																																																																																									91
D33		43																																																																																									90
VSS		44																																																																																									89
		45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88

VSS

D15

Q15

VSS

VDD

D14

Q14

D13

Q13

VSS VDD

D12

Q12

D11

Q11

VSS

VDD D10

Q10

D9

Q9

VSS

VDD

Q8 D8

Q7

D7

VSS

VDD

Q6

D6

Q5

D5

VSS

VDD

Q4

D4

Q3

D3

VSS

VDD

Q2

D2

VSS

V

Q34 D34

V

V

Q35 D35

V

V

NC A5 NC

A4 NC A3 NC

A2 NC

A1 NC

A0 V

V

A10 NC A11 NC A12 NC A13

NC A14

NC NC NC NC NC

D0 Q0 V

V

D1 Q1 V

SS

SS

DD

SS

SS

SS

DD

DD

SS

SS

MOTOROLA FAST SRAM	MCM69Q536
	3

PIN DESCRIPTIONS

Pin Locations	Symbol	Type	Description
55, 57, 59, 61, 63, 65, 68, 70, 72, 74, 76,	A0 ± A14	Input	Synchronous Address Inputs: These inputs are registered and must
143, 145, 167, 169			meet setup and hold times.
2, 6, 8, 12, 14, 18, 20, 25, 27, 31, 33, 37,	D0 ± D35	Input	Synchronous Data Input.
39, 43, 47, 51, 82, 86, 90, 94, 96, 100,
102, 106, 108, 113. 115, 119, 121, 125,
127, 131, 135, 139, 170, 174
150	E1	Input	Synchronous Chip Enable: Active low for depth expansion.
151	E2	Input	Synchronous Chip Enable: Active high for depth expansion.
152	G	Input	Asynchronous Output Enable Input:
			Low Ð enables output buffers (Qx pins).
			High Ð Qx pins are high impedance.
156	K	Input	Clock: This signal registers the address, data in, and all control signals
			except G.
146	PT	Input	Pass±through enable: Synchronous.
3, 7, 9, 13, 15, 19, 21, 24, 26, 30, 32, 36,	Q0 ± Q35	Output	Synchronous Data Output.
38, 42, 46, 50, 83, 87, 91, 95, 97, 101,
103, 107, 109, 112, 114, 118, 120, 124,
126, 130, 143, 138, 171, 175
148	W	Input	Synchronous Write.
4, 10, 16, 22, 28, 34, 40, 49, 67, 84, 98,	VDD	Supply	+ 3.3 V Power Supply.
104, 110, 116, 122, 128, 137, 155, 172
1, 5, 11, 17, 23, 29, 35, 41, 44, 45, 48,	VSS	Supply	Ground.
52, 53, 66, 85, 88, 89, 93, 99, 105, 111,
117, 123. 129, 132, 133, 136, 154, 165,
173, 176
54, 56, 58, 60, 62, 64, 69, 71, 73, 75,	NC	Ð	No Connection: There is no connection to the chip.
77 ± 81, 140, 141, 142, 144, 147, 149,
153, 157 ± 164, 166, 168

TRUTH TABLE

			Input at tn Clock				Result from tn + 1 Clock	Notes
Operation	E1	E2	W	PT		Data Input D	Data Output Q
Write and Pass±Through	L	H	L	L		D written to A	D data appears	1
Write/Read	L	H	L	H		D written to A	Q out from A	2
Pass±Through	L	H	H	L		D data	D data appears	3
Read	L	H	H	H		Don't Care	Q out from A	4
Deselected	X	L	X	X		Don't Care	Q is high±Z	5
Deselected	H	X	X	X		Don't Care	Q is high±Z	6

NOTES:

1.Write D to array and output D at Q.

2.Output contents of array to Q then write D to array.

3.Output D at Q. Do not write.

4.Output contents of array to Q. Do not write.

5.No operation.

6.No operation.

MCM69Q536	MOTOROLA FAST SRAM
4