Motorola MCM6709BRJ6, MCM6709BRJ8, MCM6709BRJ8R, MCM6709BRJ7, MCM6709BRJ6R Datasheet

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Order this document by MCM6709BR/D

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64K x 4 Bit Static RAM

The MCM6709BR is a 262,144 bit static random access memory organized as 65,536 words of 4 bits. Static design eliminates the need for external clocks or timing strobes.

Output enable (G) is a special control feature that provides increased system flexibility and eliminates bus contention problems.

The MCM6709BR meets JEDEC standards and is available in a revolutionary pinout 300 mil, 28 lead plastic surface±mount SOJ package.

•Single 5 V ± 10% Power Supply

•Fully Static Ð No Clock or Timing Strobes Necessary

•All Inputs and Outputs are TTL Compatible

•Center Power and I/O Pins for Reduced Noise

•Three State Outputs

•Fast Access Times:

MCM6709BR±6 = 6 ns

MCM6709BR±7 = 7 ns

MCM6709BR±8 = 8 ns

BLOCK DIAGRAM

A
A
A
A			MEMORY MATRIX
A	ROW	•
		•	512 ROWS x 128 x 4
	DECODER	•
A			COLUMNS

	A
	A
	A
DQ				COLUMN I/O				•
								•
•	•	INPUT						•
			COLUMN DECODER
•	•	DATA
•	•
		CONTROL
DQ
		A	A	A	A	A	A	A
E
W
G

MCM6709BR

J PACKAGE 300 MIL SOJ CASE 810B±03

PIN ASSIGNMENT

	A				1	28		A
	A				2	27		A
	A				3	26		A
	A				4	25		A
	E				5	24		G
DQ					6	23		DQ
VCC					7	22		VSS
V					8	21		VCC
SS
DQ					9	20		DQ
					10	19		A
W
	A				11	18		A
	A				12	17		A
	A				13	16		A
	A				14	15		NC

PIN NAMES

A . . . . . . . . . . . . . . . . . . . Address Inputs

W . . . . . . . . . . . . . . . . . . . . Write Enable

G . . . . . . . . . . . . . . . . . . . Output Enable

E . . . . . . . . . . . . . . . . . . . . . . Chip Enable

DQ . . . . . . . . . . . . . . . Data Input/Output

VCC . . . . . . . . . . . . + 5 V Power Supply

VSS . . . . . . . . . . . . . . . . . . . . . . . Ground

NC . . . . . . . . . . . . . . . . . No Connection

All power supply and ground pins must be connected for proper operation of the device.

This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice.

REV 2 3/17/97

MOTOROLA FAST SRAM	MCM6709BR
Motorola, Inc. 1997
	1

TRUTH TABLE (X = Don't Care)

E	G	W	Mode	Output	Cycle
H	X	X	Not Selected	High±Z	Ð
L	H	H	Read	High±Z	Ð
L	L	H	Read	Dout	Read Cycle
L	X	L	Write	Din	Write Cycle

ABSOLUTE MAXIMUM RATINGS (See Note)

Rating	Symbol	Value		Unit
Power Supply Voltage	VCC	± 0.5 to +	7.0	V
Voltage Relative to VSS for Any Pin	Vin, Vout	± 0.5 to VCC + 0.5		V
Except VCC
Output Current (per I/O)	Iout	± 30		mA
Power Dissipation	PD	2.0		W
Temperature Under Bias	Tbias	± 10 to +	85	°C
Operating Temperature	TA	0 to + 70		°C
Storage Temperature Ð Plastic	Tstg	± 55 to + 125		°C

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPER-

ATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.

This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high±impedance circuit.

This BiCMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow of at least 500 linear feet per minute is maintained.

DC OPERATING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 V ± 10%, TA = 0 to 70°C, Unless Otherwise Noted)

RECOMMENDED OPERATING CONDITIONS

Parameter	Symbol	Min	Typ	Max	Unit
Supply Voltage (Operating Voltage Range)	VCC	4.5	5.0	5.5	V
Input High Voltage	VIH	2.2	Ð	VCC + 0.3*	V
Input Low Voltage	VIL	± 0.5**	Ð	0.8	V
*VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width ≤ 2.0 ns) or I ≤ 30.0 mA.
** VIL (min) = ± 0.5 V dc @ 30.0 mA; VIL (min) = ± 2.0 V ac (pulse width ≤ 2.0 ns) or I ≤ 30.0 mA.

DC CHARACTERISTICS

Parameter	Symbol	Min	Max	Unit
Input Leakage Current (All Inputs, Vin = 0 to VCC)	Ilkg(I)	Ð	± 1.0	μA
Output Leakage Current (E = VIH, Vout = 0 to VCC)	Ilkg(O)	Ð	± 1.0	μA
Output High Voltage (IOH = ± 4.0 mA)	VOH	2.4	Ð	V
Output Low Voltage (IOL = 8.0 mA)	VOL	Ð	0.4	V

POWER SUPPLY CURRENTS

Parameter	Symbol	MCM6709BR±6	MCM6709BR±7	MCM6709BR±8	Unit	Notes
AC Active Supply Current (Iout = 0 mA, VCC = max,	ICCA	215	205	195	mA	1, 2, 3
f = fmax)
AC Standby Current (E = VIH, VCC = max, f = fmax)	ISB1	95	85	75	mA	1, 2, 3
CMOS Standby Current (VCC = max, f = 0 MHz,	ISB2	20	20	20	mA
E ≥ VCC ± 0.2 V, Vin ≤ VSS, or ≥ VCC ± 0.2 V)
NOTES:

1.Reference AC Operating Conditions and Characteristics for input and timing (VIH/VIL, tr/tf, pulse level 0 to 3.0 V, VIH = 3.0 V).

2.All addresses transition simultaneously low (LSB) and then high (MSB).

3.Data states are all zero.

MCM6709BR	MOTOROLA FAST SRAM
2

CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested)

Parameter	Symbol	Max	Unit
Address Input Capacitance	Cin	5	pF
Control Pin Input Capacitance(E, G, W)	Cin	6	pF
Input/Output Capacitance	CI/O	6	pF

AC OPERATING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted)

Input Timing Measurement Reference Level . . . . . . . . . . . .	. . . 1.5	V	Output Timing Measurement Reference Level . . . . . .	. . . . . . . 1.5 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	0 to 3.0	V	Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	See Figure 1a
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 2 ns

READ CYCLES 1 AND 2 (See Notes 1 and 2)

		MCM6709BR±6		MCM6709BR±7		MCM6709BR±8
Parameter	Symbol	Min	Max	Min	Max	Min	Max	Unit	Notes
Read Cycle Time	tAVAV	6	Ð	7	Ð	8	Ð	ns	3
Address Access Time	tAVQV	Ð	6	Ð	7	Ð	8	ns
Chip Enable Access Time	tELQV	Ð	6	Ð	7	Ð	8	ns
Output Enable Access Time	tGLQV	Ð	4	Ð	4	Ð	4	ns
Output Hold from Address Change	tAXQX	3	Ð	3	Ð	3	Ð	ns
Chip Enable Low to Output Active	tELQX	3	Ð	3	Ð	3	Ð	ns	4, 5, 6
Output Enable Low to Output Active	tGLQX	0	Ð	0	Ð	0	Ð	ns	4, 5, 6
Chip Enable High to Output High±Z	tEHQZ	Ð	3	Ð	3.5	Ð	3.5	ns	4, 5, 6
Output Enable High to Output High±Z	tGHQZ	Ð	3	Ð	3.5	Ð	3.5	ns	4, 5, 6
NOTES:

1.W is high for read cycle.

2.Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles.

3.All read cycle timings are referenced from the last valid address to the first transitioning address.

4.At any given voltage and temperature, tEHQZ max is less than tELQX min, and tGHQZ max is less than tGLQX min, both for a given device and from device to device.

5.Transition is measured 200 mV from steady±state voltage with load of Figure 1b.

6.This parameter is sampled and not 100% tested.

			+5 V
OUTPUT			480 Ω
		OUTPUT
Z0 = 50 Ω	RL = 50 Ω
		255 Ω
			5 pF
	VL = 1.5 V

(a) (b)

TIMING LIMITS

The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the system must supply at least that much time. On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never provides data later than that time.

Figure 1. AC Test Loads

MOTOROLA FAST SRAM	MCM6709BR
	3