MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document by MCM6729D/D
256K x 4 Bit Fast Static Random
Access Memory
The MCM6729D is a 1,048,576 bit static random access memory organized as 262,144 words of 4 bits. Static design eliminates the need for external clocks or timing strobes.
Output enable (G) is a special control feature that provides increased system flexibility and eliminates bus contention problems.
This device meets JEDEC standards for functionality and revolutionary pinout, and is available in a 400 mil plastic small±outline J±leaded package.
•Single 5 V ± 10% Power Supply
•Fully Static Ð No Clock or Timing Strobes Necessary
•All Inputs and Outputs Are TTL Compatible
•Three State Outputs
•Fast Access Times: 8, 10, 12 ns
•Center Power and I/O Pins for Reduced Noise
BLOCK DIAGRAM
A |
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VCC |
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VSS |
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MEMORY |
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ROW |
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MATRIX |
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DECODER |
512 ROWS x 512 x 4 |
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COLUMNS |
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A |
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A |
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A |
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DQ |
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COLUMN I/O |
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INPUT |
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COLUMN DECODER |
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DATA |
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CONTROL |
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DQ |
A |
A |
A |
A |
A |
A |
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A |
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E |
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W |
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G |
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MCM6729D
WJ PACKAGE 400 MIL SOJ CASE 857A±02
PIN ASSIGNMENT
NC |
1 |
32 |
A |
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A |
2 |
31 |
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A |
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A |
3 |
30 |
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A |
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A |
4 |
29 |
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A |
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A |
5 |
28 |
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E |
6 |
27 |
G |
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DQ |
7 |
26 |
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DQ |
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VCC |
8 |
25 |
VSS |
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VSS |
9 |
24 |
VCC |
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DQ |
10 |
23 |
DQ |
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W |
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11 |
22 |
A |
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A |
12 |
21 |
A |
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A |
13 |
20 |
A |
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A |
14 |
19 |
A |
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A |
15 |
18 |
A |
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NC |
16 |
17 |
NC |
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PIN NAMES
A . . . . . . . . . . . . . . . . . . . . . Address Input
E . . . . . . . . . . . . . . . . . . . . . . Chip Enable
W . . . . . . . . . . . . . . . . . . . . Write Enable
G . . . . . . . . . . . . . . . . . . . Output Enable
DQ . . . . . . . . . . . . . . . Data Input/Output
VCC . . . . . . . . . . . . + 5 V Power Supply
VSS . . . . . . . . . . . . . . . . . . . . . . . Ground
NC . . . . . . . . . . . . . . . . . . No Connection
10/9/96
MOTOROLA FAST SRAM |
MCM6729D |
Motorola, Inc. 1996 |
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1 |
TRUTH TABLE (X = Don't Care)
E |
G |
W |
Mode |
VCC Current |
Output |
Cycle |
H |
X |
X |
Not Selected |
ISB1, ISB2 |
High±Z |
Ð |
L |
H |
H |
Output Disabled |
ICCA |
High±Z |
Ð |
L |
L |
H |
Read |
ICCA |
Dout |
Read Cycle |
L |
X |
L |
Write |
ICCA |
High±Z |
Write Cycle |
ABSOLUTE MAXIMUM RATINGS (See Note)
Rating |
Symbol |
Value |
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Unit |
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Power Supply Voltage |
VCC |
± 0.5 to + |
7.0 |
V |
Voltage Relative to VSS for Any Pin Except |
Vin, Vout |
± 0.5 to VCC + 0.5 |
V |
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VCC |
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Output Current |
Iout |
±30 |
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mA |
Power Dissipation |
PD |
1.2 |
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W |
Temperature Under Bias |
Tbias |
± 10 to + |
85 |
°C |
Operating Temperature |
TA |
0 to + 70 |
°C |
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Storage Temperature Ð Plastic |
Tstg |
± 55 to + 125 |
°C |
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to these high±impedance circuits.
This BiCMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow of at least 500 linear feet per minute is maintained.
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 10%, TA = 0 to 70°C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
Parameter |
Symbol |
Min |
Typ |
Max |
Unit |
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Supply Voltage (Operating Voltage Range) |
VCC |
4.5 |
5.0 |
5.5 |
V |
Input High Voltage |
VIH |
2.2 |
Ð |
VCC + 0.3** |
V |
Input Low Voltage |
VIL |
± 0.5* |
Ð |
0.8 |
V |
*VIL (min) = ± 0.5 V dc; VIL (min) = ± 2.0 V ac (pulse width ≤ 2.0 ns) for I ≤ 20.0 mA.
**VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2 V ac (pulse width ≤ 2.0 ns) for I ≤ 20.0 mA.
DC CHARACTERISTICS
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Parameter |
Symbol |
Min |
Max |
Unit |
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Input Leakage Current (All Inputs, Vin = 0 to VCC) |
Ilkg(I) |
Ð |
± 1.0 |
μA |
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Output Leakage Current (E = VIH, Vout = 0 to VCC) |
Ilkg(O) |
Ð |
± 1.0 |
μA |
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Output Low Voltage (IOL = + 8.0 mA) |
VOL |
Ð |
0.4 |
V |
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Output High Voltage (IOH = ± 4.0 mA) |
VOH |
2.4 |
Ð |
V |
POWER SUPPLY CURRENTS
Parameter |
Symbol |
6729D±8 |
6729D±10 |
6729D±12 |
Unit |
Notes |
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AC Active Supply Current (Iout = 0 mA) (VCC = max, f = fmax) |
ICCA |
195 |
165 |
155 |
mA |
1, 2, 3 |
Active Quiescent Current (E = VIL, VCC = max, f = 0 MHz) |
ICC2 |
90 |
90 |
90 |
mA |
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AC Standby Current (E = VIH, VCC = max, f = fmax) |
ISB1 |
60 |
60 |
60 |
mA |
1, 2, 3 |
CMOS Standby Current (VCC = max, f = 0 MHz, E ≥ VCC ± 0.2 V, |
ISB2 |
20 |
20 |
20 |
mA |
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Vin ≤ VSS + 0.2 V, or ≥ VCC ± 0.2 V) |
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NOTES:
1.Reference AC Operating Conditions and Characteristics for input and timing (VIH/VIL, tr/tf, pulse level 0 to 3.0 V, VIH = 3.0 V).
2.All addresses transition simultaneously low (LSB) and then high (MSB).
3.Data states are all zero.
MCM6729D |
MOTOROLA FAST SRAM |
2 |
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CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested)
Parameter |
Symbol |
Typ |
Max |
Unit |
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Address Input Capacitance |
Cin |
Ð |
6 |
pF |
Control Pin Input Capacitance |
Cin |
Ð |
6 |
pF |
Input/Output Capacitance |
CI/O |
Ð |
8 |
pF |
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ±10%, TA = 0 to +70°C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . |
. . . 1.5 |
V |
Output Timing Measurement Reference Level . . . . . . |
. . . . . . . 1.5 V |
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
0 to 3.0 |
V |
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
See Figure 1a |
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . 2 ns |
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READ CYCLE TIMING (See Notes 1 and 2)
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6729D±8 |
6729D±10 |
6729D±12 |
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Parameter |
Symbol |
Min |
Max |
Min |
Max |
Min |
Max |
Unit |
Notes |
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Read Cycle Time |
tAVAV |
8 |
Ð |
10 |
Ð |
12 |
Ð |
ns |
3 |
Address Access Time |
tAVQV |
Ð |
8 |
Ð |
10 |
Ð |
12 |
ns |
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Enable Access Time |
tELQV |
Ð |
8 |
Ð |
10 |
Ð |
12 |
ns |
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Output Enable Access Time |
tGLQV |
Ð |
4 |
Ð |
5 |
Ð |
6 |
ns |
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Output Hold from Address Change |
tAXQX |
3 |
Ð |
3 |
Ð |
3 |
Ð |
ns |
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Enable Low to Output Active |
tELQX |
3 |
Ð |
3 |
Ð |
3 |
Ð |
ns |
4,5,6 |
Output Enable Low to Output Active |
tGLQX |
0 |
Ð |
0 |
Ð |
0 |
Ð |
ns |
4,5,6 |
Enable High to Output High±Z |
tEHQZ |
Ð |
4 |
Ð |
5 |
Ð |
6 |
ns |
4,5,6 |
Output Enable High to Output High±Z |
tGHQZ |
Ð |
4 |
Ð |
5 |
Ð |
6 |
ns |
4,5,6 |
NOTES: |
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1.W is high for read cycle.
2.For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycles.
3.All read cycle timings are referenced from the last valid address to the first transitioning address.
4.At any given voltage and temperature, tEHQZ (max) < tELQX (min), and tGHQZ (max) < tGLQX (min), both for a given device and from device to device.
5.Transition is measured 200 mV from steady±state voltage with load of Figure 1b.
6.This parameter is sampled and not 100% tested.
7.Device is continuously selected (E = VIL, G = VIL).
8.Addresses valid prior to or coincident with E going low.
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+5 V |
OUTPUT |
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480 Ω |
OUTPUT |
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Z0 = 50 Ω |
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R = 50 Ω |
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L |
Ω |
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255 |
5 pF |
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VL = 1.5 V |
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(a) (b)
TIMING LIMITS
The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the system must supply at least that much time. On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never provides data later than that time.
Figure 1. AC Test Loads
MOTOROLA FAST SRAM |
MCM6729D |
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3 |