Motorola MCM69L736AZP9.5, MCM69L736AZP7.5R, MCM69L736AZP8.5, MCM69L736AZP8.5R, MCM69L736AZP10.5R Datasheet

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MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

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Advance Information

4M Late Write HSTL

The MCM69L736A/818A is a 4M synchronous late write fast static RAM designed to provide high performance in secondary cache and ATM switch, Telecom, and other high speed memory applications. The MCM69L818A (organized as 256K words by 18 bits) and the MCM69L736A (organized as 128K words by 36 bits) are fabricated in Motorola's high performance silicon gate BiCMOS technology.

The differential clock (CK) inputs control the timing of read/write operations of the RAM. At the rising edge of CK, all addresses, write enables, and synchronous selects are registered. An internal buffer and special logic enable the memory to accept write data on the rising edge of CK a cycle after address and control signals. Read data is available at the falling edge of CK.

The RAM uses HSTL inputs and outputs. The adjustable input trip±point (Vref) and output voltage (VDDQ) gives the system designer greater flexibility in optimizing system performance.

The synchronous write and byte enables allow writing to individual bytes or the entire word.

The impedance of the output buffers is programmable, allowing the outputs to match the impedance of the circuit traces which reduces signal reflections.

•Byte Write Control

•Single 3.3 V +10%, ± 5% Operation

•HSTL Ð I/O (JEDEC Standard JESD8±6 Class I)

•HSTL Ð User Selectable Input Trip±Point

•HSTL Ð Compatible Programmable Impedance Output Drivers

•Register to Latch Synchronous Operation

•Asynchronous Output Enable

•Boundary Scan (JTAG) IEEE 1149.1 Compatible

•Differential Clock Inputs

•Optional x18 or x36 Organization

•MCM69L736A/818A±7.5 = 7.5 ns MCM69L736A/818A±8.5 = 8.5 ns MCM69L736A/818A±9.5 = 9.5 ns MCM69L736A/818A±10.5 = 10.5 ns

•119 Bump, 50 mil (1.27 mm) Pitch, 14 mm x 22 mm Plastic Ball Grid Array (PBGA) Package

MCM69L736A

MCM69L818A

ZP PACKAGE

PBGA

CASE 999±01

This document contains information on a new product. Specifications and information herein are subject to change without notice.

4/3/97

MOTOROLA FAST SRAM	MCM69L736A MCM69L818A
Motorola, Inc. 1997	•
	1

Motorola MCM69L736AZP9.5, MCM69L736AZP7.5R, MCM69L736AZP8.5, MCM69L736AZP8.5R, MCM69L736AZP10.5R Datasheet

		FUNCTIONAL BLOCK DIAGRAM
	ADDRESS	MEMORY	DATA IN
SA	ADDRESS	MEMORY	REGISTER
	REGISTERS	ARRAY	DQ
			DQ
			DATA OUT
			LATCH
SW	SW	CONTROL
SBx	REGISTERS	LOGIC
SBx
CK
G
SS	SS
SS	REGISTERS
	REGISTERS

PIN ASSIGNMENTS

TOP VIEW

MCM69L736A

MCM69L818A

VDDQ

VDD

VSS

DQb

VSS

DQc

DQb

DQa

DQb

DQa

DQc

VSS

DQb

VSS

VDDQ

VSS

VDDQ

VSS

VDDQ

DQc

DQb

VDDQ

DQa

SBb

DQb

VSS

DQa

DQc

SBc

DQb

SBb

DQc

VSS

DQb

VSS

DQc

DQb

DQa

VDDQ

VDD

Vref

VDD

Vref

VDD

VDDQ

DDQ

ref

DDQ

DQd

VSS

DQa

VSS

DQa

DQb

VSS

DQd

SBd

SBa

DQa

DQb

SBa

DQa

VSS

VDDQ

VSS

VDDQ

DQd

VSS

DQa

VDDQ

DQb

VSS

DQa

VSS

DQd

DQa

DQb

DQa

VSS

DQd

DQa

DQb

DQa

VDD

VSS

VDD

VSS

VDDQ

TMS

TDI

TCK

TDO

VDDQ

TMS

TDI

TCK

TDO

MCM69L736A•MCM69L818A	MOTOROLA FAST SRAM
2

MCM69L736A PIN DESCRIPTIONS

PBGA Pin Locations	Symbol	Type	Description

2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C,	SA	Input	Synchronous Address Inputs: Registered on the rising clock edge.
5C, 6C, 4N, 4P, 2R, 6R, 3T, 4T, 5T

4K	CK	Input	Address, data in, and control input register clock. Active high.

4L	CK	Input	Address, data in, and control input register clock. Active low.

4M	SW	Input	Synchronous Write: Registered on the rising clock edge, active low.
			Writes all enabled bytes.

5L, 5G, 3G, 3L	SBx	Input	Synchronous Byte Write Enable: Enables writes to byte x in
(a), (b), (c), (d)			conjunction with the SW input. Has no effect on read cycles, active
			low.

4E	SS	Input	Synchronous Chip Enable: Registered on the rising clock edge, active
			low.

4F	G	Input	Output Enable: Asynchronous pin, active low.

2U	TMS	Input	Test Mode Select (JTAG).

3U	TDI	Input	Test Data In (JTAG).

4U	TCK	Input	Test Clock (JTAG).

5U	TDO	Output	Test Data Out (JTAG).

4D	ZQ	Input	Programmable Output Impedance: Programming pin.

7T	ZZ	Input	Reserved for future use. Must be grounded.

(a) 6K, 7K, 6L, 7L, 6M, 6N, 7N, 6P, 7P	DQx	I/O	Synchronous Data I/O.
(b) 6D, 7D, 6E, 7E, 6F, 6G, 7G, 6H, 7H
(c) 1D, 2D, 1E, 2E, 2F, 1G, 2G, 1H, 2H
(d) 1K, 2K, 1L, 2L, 2M, 1N, 2N, 1P, 2P

3J, 5J	Vref	Supply	Input Reference: Provides reference voltage for input buffers.
4C, 2J, 4J, 6J, 4R, 3R	VDD	Supply	Core Power Supply.
1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U	VDDQ	Supply	Output Power Supply: Provides operating power for output buffers.
3D, 5D, 3E, 5E, 3F, 5F, 3H, 5H,	VSS	Supply	Ground.
3K, 5K, 3M, 5M, 3N, 5N, 3P, 5P, 5R

4A, 1B, 2B, 4B, 6B, 7B, 1C, 7C,	NC	Ð	No Connection: There is no connection to the chip.
4G, 4H, 1R, 7R, 1T, 2T, 6T, 6U

MOTOROLA FAST SRAM	MCM69L736A•MCM69L818A
	3

MCM69L818A PIN DESCRIPTIONS

PBGA Pin Locations	Symbol	Type	Description

2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C, 5C,	SA	Input	Synchronous Address Inputs: Registered on the rising clock edge.
6C, 4N, 4P, 2R, 6R, 2T, 3T, 5T, 6T

4K	CK	Input	Address, data in, and control input register clock. Active high.

4L	CK	Input	Address, data in, and control input register clock. Active low.

4M	SW	Input	Synchronous Write: Registered on the rising clock edge, active low.
			Writes all enabled bytes.

5L, 3G	SBx	Input	Synchronous Byte Write Enable: Enables writes to byte x in
(a), (b)			conjunction with the SW input. Has no effect on read cycles, active
			low.

4E	SS	Input	Synchronous Chip Enable: Registered on the rising clock edge, active
			low.

2U	TMS	Input	Test Mode Select (JTAG).

3U	TDI	Input	Test Data In (JTAG).

4U	TCK	Input	Test Clock (JTAG).

5U	TDO	Output	Test Data Out (JTAG).

4D	ZQ	Input	Programmable Output Impedance: Programming pin.

4F	G	Input	Output Enable: Asynchronous pin, active low.

7T	ZZ	Input	Reserved for future use. Must be grounded.

(a) 6D, 7E, 6F, 7G, 6H, 7K, 6L, 6N, 7P	DQx	I/O	Synchronous Data I/O.
(b) 1D, 2E, 2G, 1H, 2K, 1L, 2M, 1N, 2P

3J, 5J	Vref	Supply	Input Reference: Provides reference voltage for input buffers.
4C, 2J, 4J, 6J, 4R, 3R	VDD	Supply	Core Power Supply.
1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U	VDDQ	Supply	Output Power Supply: Provides operating power for output buffers.
3D, 5D, 3E, 5E, 3F, 5F, 5G, 3H, 5H,	VSS	Supply	Ground.
3K, 5K, 3L, 3M, 5M, 3N, 5N, 3P, 5P, 5R

4A, 1B, 2B, 4B, 6B, 7B, 1C, 7C,	NC	Ð	No Connection: There is no connection to the chip.
2D, 7D, 1E, 6E, 2F, 1G, 4G, 6G,
2H, 4H, 7H, 1K, 6K, 2L, 7L, 6M, 2N,
7N, 1P, 6P, 1R, 7R, 1T, 4T, 6U

MCM69L736A•MCM69L818A	MOTOROLA FAST SRAM
4

ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS, See Note 1)

Rating	Symbol	Value	Unit

Core Supply Voltage	VDD	± 0.5 to + 4.6	V
Output Supply Voltage	VDDQ	± 0.5 to VDD + 0.5	V
Voltage On Any Pin	Vin	± 0.5 to VDD + 0.5	V
Input Current (per I/O)	Iin	± 50	mA
Output Current (per I/O)	Iout	± 70	mA
Power Dissipation (See Note 2)	PD	Ð	W
Operating Temperature	TA	0 to + 70	°C
Temperature Under Bias	Tbias	±10 to + 85	°C
Storage Temperature	Tstg	± 55 to + 125	°C
NOTES:

1.Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.

2.Power dissipation capability will be dependent upon package characteristics and use environment. See enclosed thermal impedance data.

PBGA PACKAGE THERMAL CHARACTERISTICS

This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high±impedance circuit.

This BiCMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established.

This device contains circuitry that will ensure the output devices are in High±Z at power up.

Rating		Symbol	Max	Unit	Notes

Junction to Ambient (Still Air)		RθJA	53	°C/W	1, 2
Junction to Ambient (@200 ft/min)	Single Layer Board	RθJA	38	°C/W	1, 2
Junction to Ambient (@200 ft/min)	Four Layer Board	RθJA	22	°C/W
Junction to Board (Bottom)		RθJB	14	°C/W	3
Junction to Case (Top)		RθJC	5	°C/W	4
NOTES:

1.Junction temperature is a function of on±chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.

2.Per SEMI G38±87.

3.Indicates the average thermal resistance between the die and the printed circuit board.

4.Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC±883 Method 1012.1).

MOTOROLA FAST SRAM	MCM69L736A•MCM69L818A
	5

DC OPERATING CONDITIONS AND CHARACTERISTICS

(0_C ≤ TA ≤ 70_C, Unless Otherwise Noted)

RECOMMENDED OPERATING CONDITIONS (See Notes 1 through 4)

				Typical	Typical	Typical	Typical
Parameter		Symbol	Min	±7.5	±8.5	±9.5	±10.5	Max	Unit	Notes

Input Reference DC Voltage		Vref (dc)	0.6	Ð	Ð	Ð	Ð	1.1	V	11
Core Power Supply Voltage		VDD	3.15	Ð	Ð	Ð	Ð	3.6	V
Output Driver Supply Voltage		VDDQ	1.4	Ð	Ð	Ð	Ð	1.6	V
Active Power Supply Current	(x18)	IDD1	Ð	300	290	270	260	450	mA	5
	(x36)		Ð	390	380	360	350	560

Quiescent Active Power Supply Current)		IDD2	Ð	190	190	190	190	250	mA	6, 10
Active Standby Power Supply Current		ISB1	Ð	160	160	160	160	250	mA	7
Quiescent Standby Power Supply Current		ISB2	Ð	140	140	140	140	230	mA	8, 10
Sleep Mode Power Supply Current		ISB3	Ð	TBD	TBD	TBD	TBD	TBD	mA	9, 10
NOTES:

1.All data sheet parameters specified to full range of VDD unless otherwise noted. All voltages are referenced to voltage applied to VSS bumps.

2.Supply voltage applied to VDD connections.

3.Supply voltage applied to VDDQ connections.

4.All power supply currents measured with outputs open or deselected.

5.VDD = VDD (max), tKHKH = tKHKH (min), SS registered active, 50% read cycles.

6.VDD = VDD (max), tKHKH = dc, SS registered active.

7.VDD = VDD (max), tKHKH = tKHKH (min), SS registered inactive.

8.VDD = VDD (max), tKHKH = dc, SS registered inactive, ZZ low.

9.VDD = VDD (Max), tKHKH = dc, registered inactive, ZZ high.

10.200 mV ≥ Vin ≥ VDDQ ± 200 mV.

11.Although considerable latitude in the selection of the nominal dc value (i.e., rms value) of Vref is supported, the peak to peak ac component superimposed on Vref may not exceed 5% of the dc component of Vref.

DC INPUT CHARACTERISTICS

Parameter	Symbol	Min	Max	Unit	Notes

DC Input Logic High	VIH (dc)	Vref + 0.1	VDD + 0.3	V
DC Input Logic Low	VIL (dc)	± 0.3	Vref ± 0.1	V	1
Input Reference DC Voltage	Vref (dc)	0.6	1.1	V	2
Input Leakage Current	Ilkg(1)	Ð	± 5	μA	3
Clock Input Signal Voltage	Vin	± 0.3	VDD + 0.3	V
Clock Input Differential Voltage	VDIF (dc)	0.1	VDD + 0.6	V	4
Clock Input Common Mode Voltage Range (See Figure 3)	VCM (dc)	0.68	1.1	V	5
Clock Input Crossing Point Voltage Range	VX	0.68	1.1	V
NOTES:

1.Inputs may undershoot to ± 0.5 V (peak) for up to 20% tKHKH (e.g., 2 ns at a clock cycle time of 10 ns).

2.Although considerable latitude in the selection of the nominal dc value (i.e., rms value) of Vref is supported, the peak±to±peak ac component superimposed on Vref may not exceed 5% of the dc component of Vref.

3.0 V ≤ Vin ≤ VDDQ for all pins.

4.Minimum instantaneous differential input voltage required for differential input clock operation.

5.Maximum rejectable common mode input voltage variation.

MCM69L736A•MCM69L818A	MOTOROLA FAST SRAM
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