Motorola MCM6226BBXJ35, MCM6226BBXJ35R2, MCM6226BBXJ20, MCM6226BBXJ20R2, MCM6226BBXJ25 Datasheet

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Order this document by MCM6226BB/D

128K x 8 Bit Static Random

Access Memory

The MCM6226BB is a 1,048,576 bit static random access memory organized as 131,072 words of 8 bits. Static design eliminates the need for external clocks or timing strobes while CMOS circuitry reduces power consumption and provides for greater reliability.

The MCM6226BB is equipped with both chip enable (E1 and E2) and output enable (G) pins, allowing for greater system flexibility and eliminating bus contention problems.

The MCM6226BB is available in 300 mil and 400 mil, 32 lead surface±mount SOJ packages.

•Single 5 V ± 10% Power Supply

•Fast Access Times: 15/17/20/25/35 ns

•Equal Address and Chip Enable Access Times

•All Inputs and Outputs are TTL Compatible

•Three State Outputs

•Low Power Operation: 190/180/165/150/130 mA Maximum, Active AC

BLOCK DIAGRAM

	A
	A
	A
	A		MEMORY MATRIX
		ROW
	A		512 ROWS x
		DECODER
			2048 COLUMNS
	A
	A
	A
	A
	DQ	INPUT	COLUMN I/O
	DQ	DATA
		CONTROL	COLUMN DECODER
	E1		A A A A A A A A
	E2
	W
	G

MCM6226BB

XJ PACKAGE 400 MIL SOJ CASE 857A±02

EJ PACKAGE 300 MIL SOJ CASE 857±02

PIN ASSIGNMENT

NC		1		32		VCC
A		2		31		A
A		3		30			E2
A		4		29		W
A		5		28			A
A		6		27		A
A		7		26		A
A		8		25		A
A		9		24		G
A		10		23		A
		11		22
A						E1
A		12		21			DQ
DQ		13		20			DQ
DQ		14		19			DQ
DQ		15		18			DQ
VSS							DQ
		16		17

PIN NAMES

A . . . . . . . . . . . . . . . . . . . . Address Inputs

W . . . . . . . . . . . . . . . . . . . . . Write Enable

G . . . . . . . . . . . . . . . . . . . Output Enable

E1, E2 . . . . . . . . . . . . . . . . Chip Enables

DQ . . . . . . . . . . . . . Data Inputs/Outputs

NC . . . . . . . . . . . . . . . . . . No Connection

VCC . . . . . . . . . . . . . + 5 V Power Supply

VSS . . . . . . . . . . . . . . . . . . . . . . . . Ground

REV 2 10/31/96

MOTOROLAMotorola, Inc. 1996FAST SRAM

1

TRUTH TABLE

E1	E2	G	W	Mode	I/O Pin	Cycle	Current
H	X	X	X	Not Selected	High±Z	Ð	ISB1, ISB2
X	L	X	X	Not Selected	High±Z	Ð	ISB1, ISB2
L	H	H	H	Output Disabled	High±Z	Ð	ICCA
L	H	L	H	Read	Dout	Read	ICCA
L	H	X	L	Write	Din	Write	ICCA

H = High, L = Low, X = Don't Care

ABSOLUTE MAXIMUM RATINGS (See Note)

Rating	Symbol	Value	Unit
Power Supply Voltage Relative to VSS	VCC	± 0.5 to 7.0	V
Voltage Relative to VSS for Any Pin	Vin, Vout	± 0.5 to VCC + 0.5	V
Except VCC
Output Current (per I/O)	Iout	± 20	mA
Power Dissipation	PD	1.0	W
Temperature Under Bias	Tbias	± 10 to + 85	°C
Operating Temperature	TA	0 to + 70	°C
Storage Temperature	Tstg	± 55 to + 150	°C

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPER-

ATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.

This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to these high±impedance circuits.

This CMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow of at least 500 linear feet per minute is maintained.

DC OPERATING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 V ± 10%, TA = 0 to 70°C, Unless Otherwise Noted)

RECOMMENDED OPERATING CONDITIONS

Parameter	Symbol	Min	Max	Unit
Supply Voltage (Operating Voltage Range)	VCC	4.5	5.5	V
Input High Voltage	VIH	2.2	VCC + 0.3**	V
Input Low Voltage	VIL	± 0.5*	0.8	V

*VIL (min) = ± 0.5 V dc; VIL (min) = ± 2.0 V ac (pulse width ≤ 20 ns).

**VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2 V ac (pulse width ≤ 20 ns).

DC CHARACTERISTICS AND SUPPLY CURRENTS

		Parameter		Symbol	Min	Max	Unit
Input Leakage Current (All Inputs, Vin = 0 to VCC)				Ilkg(I)	Ð	± 1	μA
Output Leakage Current (E* = VIH, Vout = 0 to VCC)				Ilkg(O)	Ð	± 1	μA
AC Active Supply Current (Iout = 0 mA, all inputs =			MCM6226BB±15: tAVAV = 15 ns	ICCA	Ð	195	mA
VIL or VIH, VIL = 0, VIH ≥ 3 V, cycle time ≥ tAVAV min,			MCM6226BB±17: tAVAV = 17 ns		Ð	180
VCC = max)			MCM6226BB±20: tAVAV = 20 ns		Ð	165
			MCM6226BB±25: tAVAV = 25 ns		Ð	150
			MCM6226BB±35: tAVAV = 35 ns		Ð	130
AC Standby Current (VCC = max, E* = VIH, f = fmax)			MCM6226BB±15: tAVAV = 15 ns	ISB1	Ð	45	mA
			MCM6226BB±17: tAVAV = 17 ns		Ð	40
			MCM6226BB±20: tAVAV = 20 ns		Ð	35
			MCM6226BB±25: tAVAV = 25 ns		Ð	30
			MCM6226BB±35: tAVAV = 35 ns		Ð	25
CMOS Standby Current (E* ≥ VCC ± 0.2 V, Vin ≤ VSS + 0.2 V				ISB2	Ð	5	mA
or ≥ VCC ± 0.2 V, VCC = max, f = 0 MHz)
Output Low Voltage (IOL = + 8.0 mA)				VOL	Ð	0.4	V
Output High Voltage (IOH = ± 4.0 mA)				VOH	2.4	Ð	V

*E1 and E2 are represented by E in this data sheet. E2 is of opposite polarity to E1.

MCM6226BB	MOTOROLA FAST SRAM
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CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested)

	Characteristic			Symbol	Typ	Max	Unit
Input Capacitance	All Inputs Except Clocks	and DQs		Cin	4	6	pF
	E1, E2, G, and W			Cck	5	8
I/O Capacitance			DQ	CI/O	5	8	pF

AC OPERATING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted)

Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	0 to 3.0	V	Output Timing Measurement Reference Level . . . . . .	. . . . . . . 1.5 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 2 ns		Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	See Figure 1a
Input Timing Measurement Reference Level . . . . . . . . . . . .	. . . 1.5	V

READ CYCLE TIMING (See Notes 1, 2, and 3)

6226BB±15

6226BB±17

6226BB±20

6226BB±25

6226BB±35

Parameter

Symbol

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Unit

Notes

Read Cycle Time

tAVAV

15

Ð

17

Ð

20

Ð

25

Ð

35

Ð

ns

4

Address Access Time

tAVQV

Ð

15

Ð

17

Ð

20

Ð

25

Ð

35

ns

Enable Access Time

tELQV

Ð

15

Ð

17

Ð

20

Ð

25

Ð

35

ns

5

Output Enable Access Time

tGLQV

Ð

6

Ð

7

Ð

7

Ð

8

Ð

8

ns

Output Hold from Address

tAXQX

3

Ð

3

Ð

3

Ð

3

Ð

3

Ð

ns

Change

Enable Low to Output Active

tELQX

5

Ð

5

Ð

5

Ð

5

Ð

5

Ð

ns

6, 7, 8

Output Enable Low to Output

tGLQX

0

Ð

0

Ð

0

Ð

0

Ð

0

Ð

ns

6, 7, 8

Active

Enable High to Output High±Z

tEHQZ

Ð

6

Ð

7

Ð

7

Ð

8

Ð

8

ns

6, 7, 8

Output Enable High to Output

tGHQZ

Ð

6

Ð

7

Ð

7

Ð

8

Ð

8

ns

6, 7, 8

High±Z

NOTES:

1.W is high for read cycle.

2.Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus con- tention conditions during read and write cycles.

3.E1 and E2 are represented by E in this data sheet. E2 is of opposite polarity to E1.

4.All timings are referenced from the last valid address to the first transitioning address.

5.Addresses valid prior to or coincident with E going low.

6.At any given voltage and temperature, tEHQZ max is less than tELQX min, and tGHQZ max is less than tGLQX min, both for a given device and from device to device.

7.Transition is measured ± 500 mV from steady±state voltage with load of Figure 1b.

8.This parameter is sampled and not 100% tested.

9.Device is continuously selected (E ≤ VIL, G ≤ VIL).

			+5 V
OUTPUT			480 Ω
		OUTPUT
Z0 = 50 Ω	RL = 50 Ω
		255 Ω
			5 pF
	VL = 1.5 V

(a) (b)

TIMING LIMITS

The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the system must supply at least that much time. On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never provides data later than that time.

Figure 1. AC Test Loads

MOTOROLA FAST SRAM	MCM6226BB
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