Motorola MCM69P618CTQ7, MCM69P618CTQ7R, MCM69P618CTQ5, MCM69P618CTQ5R, MCM69P618CTQ6 Datasheet

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Order this document by MCM69P618C/D

64K x 18 Bit Pipelined BurstRAM

Synchronous Fast Static RAM

The MCM69P618C is a 1M±bit synchronous fast static RAM designed to provide a burstable, high performance, secondary cache for the 68K Family, PowerPC , 486, i960 , and Pentium microprocessors. It is organized as 64K words of 18 bits each. This device integrates input registers, an output register, a 2±bit address counter, and high speed SRAM onto a single monolithic circuit for reduced parts count in cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K). BiCMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability.

Addresses (SA), data inputs (DQx), and all control signals except output enable (G) and Linear Burst Order (LBO) are clock (K) controlled through positive±edge±triggered noninverting registers.

Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst addresses can be generated internally by the MCM69P618C (burst sequence operates in linear or interleaved mode dependent upon the state of LBO) and controlled by the burst address advance (ADV) input pin.

Write cycles are internally self±timed and initiated by the rising edge of the clock (K) input. This feature eliminates complex off±chip write pulse generation and provides increased timing flexibility for incoming signals.

Synchronous byte write (SBx), synchronous global write (SGW), and synchronous write enable SW are provided to allow writes to either individual bytes or to both bytes. The two bytes are designated as ªaº and ªbº. SBacontrols DQa and SBb controls DQb. Individual bytes are written if the selected byte writes SBx are asserted with SW. Both bytes are written if either SGW is asserted or if both SBx and SW are asserted.

For read cycles, pipelined SRAMs output data is temporarily stored by an edge±triggered output register and then released to the output buffers at the next rising edge of clock (K).

The MCM69P618C operates from a single 3.3 V power supply and all inputs and outputs are LVTTL compatible and 5 V tolerant.

•MCM69P618C±4 = 4 ns Access / 7.5 ns Cycle MCM69P618C±4.5 = 4.5 ns Access / 8 ns Cycle MCM69P618C±5 = 5 ns Access / 10 ns Cycle MCM69P618C±6 = 6 ns Access / 12 ns Cycle MCM69P618C±7 = 7 ns Access / 13.3 ns Cycle

•Single 3.3 V + 10%, ± 5% Power Supply

•ADSP, ADSC, and ADV Burst Control Pins

•Selectable Burst Sequencing Order (Linear/Interleaved)

•Internally Self±Timed Write Cycle

•Byte Write and Global Write Control

•Single±Cycle Deselect Timing

•5 V Tolerant on all Pins (Inputs and I/Os)

•100±Pin TQFP Package

MCM69P618C

TQ PACKAGE

TQFP

CASE 983A±01

The PowerPC name is a trademark of IBM Corp., used under license therefrom. i960 and Pentium are trademarks of Intel Corp.

REV 2 2/16/98

MOTOROLA FAST SRAM	MCM69P618C
Motorola, Inc. 1998
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FUNCTIONAL BLOCK DIAGRAM

LBO
ADV
K		BURST	2	16
					64K x 18 ARRAY
ADSC		COUNTER
	K2
		CLR
ADSP
SA		2
	ADDRESS	16	14
SA1
SA0	REGISTER
SGW
SW	WRITE			18	18
	REGISTER
SBa	a

		2
	WRITE	DATA±IN	DATA±0UT
		REGISTER	REGISTER
	REGISTER	K
SBb	b

		K2	K
	SE1	ENABLE	ENABLE
	SE2
		REGISTER	REGISTER
	SE3
	G

DQa, DQb

MCM69P618C	MOTOROLA FAST SRAM
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PIN ASSIGNMENT

SA SA SE1 SE2

NC NC

SBb SBa

SE3

V

V K

SGW SW G

ADSC

ADSP ADV SA SA

DD

SS

NC		100 99 98							97 96				95 94 93 92 91										90 89				88 87 86 85 84 83 82									81
		1																																		80
NC		2																																		79
NC		3
																																				78
VDD		4																																		77
VSS		5																																		76
NC
		6																																		75
NC
		7																																		74
DQb		8																																		73
DQb		9																																		72
VSS		10																																		71
VDD		11																																		70
DQb		12																																		69
DQb		13																																		68
NC		14																																		67
VDD		15																																		66
NC		16																																		65
VSS		17																																		64
DQb		18																																		63
DQb		19																																		62
VDD		20																																		61
VSS		21																																		60
DQb		22																																		59
DQb		23
																																				58
DQb		24
																																				57
NC		25																																		56
VSS		26																																		55
VDD		27																																		54
NC		28																																		53
NC		29																																		52
NC		30																																		51
		31 32 33 34 35 36 37 38 39 40 41 42																									43 44 45 46 47 48 49									50
			LBO SA SA						SA SA				SA1 SA0 NC NC V										V NC				NC SA SA SA SA SA NC									NC
																					SS		DD

SA

NC

NC

VDD VSS

NC

DQa DQa DQa

VSS VDD

DQa

DQa VSS

NC

VDD

NC

DQa DQa

VDD VSS DQa

DQa

NC

NC

VSS VDD

NC

NC

NC

MOTOROLA FAST SRAM	MCM69P618C
	3

PIN DESCRIPTIONS

Pin Locations

Symbol

Type

Description

85

Input

Synchronous Address Status Controller: Initiates READ, WRITE, or

ADSC

chip deselect cycle.

84

Input

Synchronous Address Status Processor: Initiates READ, WRITE, or

ADSP

chip deselect cycle (exception Ð chip deselect does not occur when

is asserted and

is high).

ADSP

SE1

83

Input

Synchronous Address Advance: Increments address count in

ADV

accordance with counter type selected (linear/interleaved).

(a) 58, 59, 62, 63, 68, 69, 72, 73, 74

DQx

I/O

Synchronous Data I/O: ªxº refers to the byte being read or written

(b) 8, 9, 12, 13, 18, 19, 22, 23, 24

(byte a, b).

86

Input

Asynchronous Output Enable Input:

G

Low Ð enables output buffers (DQx pins).

High Ð DQx pins are high impedance.

89

K

Input

Clock: This signal registers the address, data in, and all control signals

except

G

and

LBO.

31

Input

Linear Burst Order Input: This pin must remain in steady state (this

LBO

signal not registered or latched). It must be tied high or low.

Low Ð linear burst counter (68K/PowerPC).

High Ð interleaved burst counter (486/i960/Pentium).

32, 33, 34, 35, 44, 45, 46,

SA

Input

Synchronous Address Inputs: These inputs are registered and must

47, 48, 80, 81, 82, 99, 100

meet setup and hold times.

36, 37

SA1,SA0

Input

Synchronous Address Inputs: These pins must be wired to the two

LSBs of the address bus for proper burst operation. These inputs are

registered and must meet setup and hold times.

93, 94

Input

Synchronous Byte Write Inputs: ªxº refers to the byte being written (byte

SBx

(a) (b)

a, b).

SGW

overrides

SBx.

98

Input

Synchronous Chip Enable: Active low to enable chip.

SE1

Negated high±blocks

ADSP

or deselects chip when

ADSC

is asserted.

97

SE2

Input

Synchronous Chip Enable: Active high for depth expansion.

92

Input

Synchronous Chip Enable: Active low for depth expansion.

SE3

88

Input

Synchronous Global Write: This signal writes all bytes regardless of the

SGW

status of the

SBx

and

SW

signals. If only byte write signals

SBx

are

being used, tie this pin high.

87

Input

Synchronous Write: This signal writes only those bytes that have been

SW

selected using the byte write

SBx

pins. If only byte write signals

SBx

are being used, tie this pin low.

4, 11, 15, 20, 27, 41, 54,

VDD

Supply

Power Supply: 3.3 V + 10%, ± 5%.

61, 65, 70, 77, 91

5, 10, 17, 21, 26, 40, 55,

VSS

Supply

Ground.

60, 67, 71, 76, 90

64

NC

Input

No Connection: There is no connection to the chip. For compatibility

reasons, it is recommended that this pin be tied low for system designs

that do not have a sleep mode associated with the cache/memory

controller. Other vendors' RAMs may have implemented the Sleep

Mode (ZZ) feature.

1, 2, 3, 6, 7, 14, 16, 25, 28, 29, 30,

NC

Ð

No Connection: There is no connection to the chip.

38, 39, 42, 43, 49, 50, 51, 52,

53, 56, 57, 66, 75, 78, 79, 95, 96

MCM69P618C	MOTOROLA FAST SRAM
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