Motorola MCM69D536TQ6R, MCM69D536TQ8, MCM69D536TQ8R, MCM67J618AFN5, MCM69D536TQ6 Datasheet

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Order this document by MCM69D536/D

32K x 36 Bit Synchronous

Dual I/O, Dual Address SRAM

The MCM69D536 is a 1M±bit static random access memory, organized as 32K words of 36 bits. It features common data input and data output buffers and incorporates input and output registers on±board with high speed SRAM.

The MCM69D536 allows the user to concurrently perform reads, writes, or pass±through cycles in combination on the two data ports. The two address ports (AX, AY) determine the read or write locations for their respective data ports (DQX, DQY).

The synchronous design allows for precise cycle control with the use of an external single clock (K). All signal pins except output enables (GX, GY) are registered on the rising edge of clock (K).

The pass±through feature allows data to be passed from one port to the other, in either direction. The PTX input must be asserted to pass data from port X to port Y. The PTY will likewise pass data from port Y to port X. A pass±through operation takes precedence over a read operation.

For the case when AX and AY are the same, certain protocols are followed. If both ports are read, the reads occur normally. If one port is written and the other is read, the read from the array will occur before the data is written. If both ports are written, only the data on DQY will be written to the array.

•Single 3.3 V ± 5% Power Supply

•Fast Access Times: 6/8 ns Max

•Throughput of 2.98 Gigabits/Second

•Single Clock Operation

•Address, Data Input, E1, E2, PTX, PTY, WX, WY, and Data Output Registers On±Chip

•83 MHz Maximum Clock Frequency

•Self±Timed Write

•Two Bi±Directional Data Buses

•Can be Configured as Separate I/O

•Pass±Through Feature

•Asynchronous Output Enables (GX, GY)

•LVTTL Compatible I/O

•Concurrent Reads and Writes

•176±Pin TQFP Package

Suggested Applications
Ð ATM	Ð Ethernet Switches	Ð Routers
Ð Cell/Frame Buffers	Ð SNA Switches	Ð Shared Memory

MCM69D536

TQ PACKAGE 176 LEAD TQFP CASE 1101±01

Product Family Configurations

Part	Dual	Single	Dual	Separate
Number	Address	Address	I/O	I/O	Configuration	VDD
MCM69D536	n	Note 1	n	Note 2	32K x 36	3.3 V
MCM69D618	n	Note 1	n	Note 2	64K x 18	3.3 V
MCM67Q709A					128K x 9	5.0 V
MCM67Q909					512K x 9	5.0 V
NOTES:

1.Tie AX and AY address ports together for the part to function as a single address part.

2.Tie GX high for DQX to be inputs and tie WY high and GY low for DQY to be outputs.

REV 4 1/16/98

MOTOROLA FAST SRAM	MCM69D536
Motorola, Inc. 1998
	1

BLOCK DIAGRAM

15	ADDRESS	32K x 36 ARRAY	ADDRESS	15
AX	REGISTER		REGISTER	AY

WX	WRITE X	WRITE	SENSE	SENSE	WRITE	WRITE Y	WY
	REGISTER	DRIVER	AMPS	AMPS	DRIVER	REGISTER
PTX	PTX		PASS±THROUGH			PTY	PTY
	REGISTER					REGISTER
K		DATA IN	OUTPUT	OUTPUT	DATA IN	K
		REGISTER	REGISTER	REGISTER	REGISTER
E1	ENABLE
E2	REG 1

ENABLE
REG 2	DQX	DQY

GX

GY

MCM69D536	MOTOROLA FAST SRAM
2

PIN ASSIGNMENT

			V		DQY19	DQX19	V	V	DQY18	DQX18	AX6	AY6		AX7	AY7	V	NC NC			NC	NC NC		NC NC		NC	K V		V	GY	GX	E2	E1	WY	WX	PTY		PTX AX8		AY8		AX9	AY9	NC	NC	DQX17	DQY17	V	V	DQX16	DQY16		V
			SSi				SS	DD								SSi											DD SS																				DD	SS				SSi
VSSi		176			175	174	173	172	171	170	169	168	167		166	165	164	163		162	161	160	159	158	157	156	155	154	153	152	151	150	149	148	147	146		145	144	143		142	141	140	139	138	137	136	135	134		133
		1																																																		132
DQX20		2																																																		131
DQY20		3																																																		130
VDD		4																																																		129
VSS		5																																																		128
DQX21		6																																																		127
DQY21		7																																																		126
DQX22		8																																																		125
DQY22		9																																																		124
VDD		10																																																		123
VSS		11																																																		122
DQX23		12																																																		121
DQY23		13																																																		120
																																																				119
DQX24		14
DQY24		15																																																		118
VDD		16																																																		117
VSS		17																																																		116
DQX25		18																																																		115
DQY25		19																																																		114
DQX26		20																																																		113
DQY26		21																																																		112
VDD		22																																																		111
VSS		23																																																		110
DQY27		24																																																		109
DQX27		25																																																		108
DQY28		26																																																		107
DQX28		27																																																		106
VDD		28																																																		105
VSS		29																																																		104
DQY29		30																																																		103
DQX29		31																																																		102
DQY30		32																																																		101
DQX30		33																																																		100
VDD		34																																																		99
																																																				98
VSS		35
DQY31		36																																																		97
DQX31		37																																																		96
DQY32		38																																																		95
DQX32		39																																																		94
VDD		40																																																		93
VSS		41																																																		92
DQY33		42																																																		91
DQX33		43																																																		90
VSSi		44																																																		89
		45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 6162 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88

VSSi

DQX15

DQY15

VSS

VDD

DQX14

DQY14

DQX13

DQY13

VSS

VDD

DQX12

DQY12

DQX11

DQY11

VSS

VDD

DQX10

DQY10

DQX9

DQY9

VSS

VDD

DQY8

DQX8

DQY7

DQX7

VSS

VDD DQY6

DQX6

DQY5

DQX5

VSS

VDD DQY4

DQX4

DQY3

DQX3

VSS

VDD DQY2

DQX2 VSSi

V

DQY34 DQX34

V

V

DQY35 DQX35

V

V

AY5 AX5 AY4 AX4 AY3 AX3 AY2 AX2

AY1 AX1 AY0 AX0 V

V

AX10 AY10 AX11 AY11

AX12 AY12 AX13 AY13 AX14 AY14 NC NC NC NC

DQX0

DQY0

V

V

DQX1 DQY1

V

SSi

SS

DD

SSi

SSi

SS

DD

DD

SS

SSi

MOTOROLA FAST SRAM	MCM69D536
	3

PIN DESCRIPTIONS

Pin Locations	Symbol	Type	Description
65, 63, 61, 59, 57, 55, 169, 167,	AX0 ±	Input	Address Port X. Never allow floating addresses for inputs AX0 ± AX14.
145, 143, 68, 70, 72, 74, 76	AX14		A pullup resistor is needed.
64, 62, 60, 58, 56, 54, 168, 166,	AY0 ±	Input	Address Port Y. Never allow floating addresses for inputs AY0 ± AY14.
144, 142, 69, 71, 73, 75, 77	AY14		A pullup resistor is needed.
82, 86, 90, 94, 96, 100, 102, 106, 108,	DQX0 ±	I/O	Data Input/Output Port X.
113. 115, 119, 121, 125, 127, 131,	DQX35
135, 139, 170, 174, 2, 6, 8, 12, 14, 18,
20, 25, 27, 31, 33, 37, 39, 43, 47, 51
83, 87, 91, 95, 97, 101, 103, 107, 109,	DQY0 ±	I/O	Data Input/Output Port Y.
112, 114, 118, 120, 124, 126, 130, 134,	DQY35
138, 171, 175, 3, 7, 9, 13, 15, 19, 21,
24, 26, 30, 32, 36, 38, 42, 46, 50
150	E1	Input	Synchronous Chip Enable: Active low.
151	E2	Input	Synchronous Chip Enable: Active high.
152	GX	Input	Asynchronous Output Enable Port X Input:
			Low Ð enables output buffers (DQXx pins).
			High Ð DQXx pins are high impedance.
153	GY	Input	Asynchronous Output Enable Port Y Input:
			Low Ð enables output buffers (DQYx pins).
			High Ð DQYx pins are high impedance.
156	K	Input	Clock: This signal registers the address, data in, and all control signals
			except G.
146	PTX	Input	Pass±Through Port X.
147	PTY	Input	Pass±Through Port Y.
148	WX	Input	Synchronous Write Enable Port X.
149	WY	Input	Synchronous Write Enable Port Y.
4, 10, 16, 22, 28, 34, 40, 49,	VDD	Supply	+ 3.3 V Power Supply.
67, 84, 92, 98, 104, 110,
116, 122, 128, 137, 155, 172
5, 11, 17, 23, 29, 35, 41, 48,	VSS	Supply	Ground.
66, 85, 93, 99, 105, 111,
117, 123. 129, 136, 154, 173
1, 44, 45, 52, 53, 88,	VSSi	Input	Bonded to die flag. No chip current flows through these pins.
89, 132, 133, 165, 176
78± 81, 140, 141, 157 ± 164	NC	Ð	No Connection: There is no connection to the chip.

MCM69D536	MOTOROLA FAST SRAM
4

TRUTH TABLE (See Notes 1 through 5)

					Input at tn Clock
Operation Number	E1	E2	WX	WY	PTX	PTY	Operation
1	H	X	X	X	X	X	Deselected
2	X	L	X	X	X	X	Deselected
3	L	H	0	X	X	X	Write X Port
4	L	H	X	0	X	X	Write Y Port
5	L	H	X	X	0	X	Pass±Through X to Y
6	L	H	X	X	X	0	Pass±Through Y to X
7	L	H	1	X	1	1	Read X
8	L	H	X	1	1	1	Read Y

NOTES:

1.GX/GY must be controlled to avoid bus contention issues during write and pass±through cycles.

2.Operation numbers 3 ± 6 can be used in any combination.

3.Operation numbers 4 and 7, 3 and 8, 7 and 8 can be combined.

4.Operation number 5 can not be combined with operation number 7 or 8 because pass±through takes precedence over a read operation.

5.Operation number 6 can not be combined with operation number 7 or 8 because pass±through takes precedence over a read operation.

tn		tn + 1

K

ADDRESS & CONTROL

VALID

PIPELINED READ ACCESS

DATA INPUT D

VALID

PASS±THROUGH

DATA OUTPUT Q

ABSOLUTE MAXIMUM RATINGS (See Note)

Rating	Symbol	Value		Unit
Power Supply Voltage	VDD	± 0.5 to +	4.6	V
Voltage Relative to VSS for Any Pin	Vin, Vout	± 0.5 to VDD + 0.5		V
Except VDD
Output Current	Iout	± 20		mA
Power Dissipation	PD	TBD		W
Temperature Under Bias	Tbias	± 10 to +	85	°C
Operating Temperature	TA	0 to + 70		°C
Storage Temperature Ð Plastic	Tstg	± 55 to + 125		°C

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.

VALID

This is a synchronous device. All synchronous inputs must meet specified setup and hold times with stable logic levels for ALL rising edges of clock (K) while the device is selected.

This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to these high±impedance circuits.

MOTOROLA FAST SRAM	MCM69D536
	5