Motorola MCM6246WJ20, MCM6246WJ17, MCM6246WJ17R2, MCM6246WJ35R2, MCM6246WJ20R2 Datasheet

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Order this document by MCM6246/D

512K x 8 Bit Static Random

Access Memory

The MCM6246 is a 4,194,304 bit static random access memory organized as 524,288 words of 8 bits. Static design eliminates the need for external clocks or timing strobes, while CMOS circuitry reduces power consumption and provides for greater reliability.

The MCM6246 is equipped with chip enable (E) and output enable (G) pins, allowing for greater system flexibility and eliminating bus contention problems. Either input, when high, will force the outputs into high impedance.

The MCM6246 is available in a 400 mil, 36±lead surface±mount SOJ package.

•Single 5 V ± 10% Power Supply

•Fast Access Time: 17/20/25/35 ns

•Equal Address and Chip Enable Access Time

•All Inputs and Outputs are TTL Compatible

•Three±State Outputs

•Power Operation: 205/200/185/170 mA Maximum, Active AC

			BLOCK DIAGRAM
	A
	A
	A
	A
	A	ROW	MEMORY MATRIX
			1024 ROWS x
	A	DECODER
			4096 COLUMNS
	A
	A
	A
	A

DQ			COLUMN I/O
INPUT			COLUMN DECODER
DATA
CONTROL
DQ
A	A	A	A	A	A	A	A	A

DQ

E

	W	DQ
	G

MCM6246

WJ PACKAGE 400 MIL SOJ CASE 893±01

PIN ASSIGNMENT

		A			1	36		NC
		A			2	35		A
					3			A
		A				34
		A			4	33		A
		A			5	32		A
		E			6	31		G
DQ					7	30		DQ
DQ					8	29		DQ
VCC					9	28		VSS
VSS					10	27		VCC
DQ					11	26		DQ
DQ					12	25		DQ
								A
W					13	24
								A
		A			14	23
		A			15	22		A
		A			16	21		A
		A			17	20		A
		A			18	19		NC

PIN NAMES

A . . . . . . . . . . . . . . . . . . . Address Inputs

W . . . . . . . . . . . . . . . . . . . . Write Enable

G . . . . . . . . . . . . . . . . . . . Output Enable

E . . . . . . . . . . . . . . . . . . . . . . Chip Enable

DQ . . . . . . . . . . . . . . . Data Input/Output

NC . . . . . . . . . . . . . . . . . No Connection

VCC . . . . . . . . . . . . + 5 V Power Supply

VSS . . . . . . . . . . . . . . . . . . . . . . . Ground

REV 5 6/9/97

Motorola, Inc. 1997	MCM6246
MOTOROLA FAST SRAM
	1

TRUTH TABLE (X = Don't Care)

E	G	W	Mode	I/O Pin	Cycle	Current
H	X	X	Not Selected	High±Z	Ð	ISB1, ISB2
L	H	H	Output Disabled	High±Z	Ð	ICCA
L	L	H	Read	Dout	Read	ICCA
L	X	L	Write	High±Z	Write	ICCA

ABSOLUTE MAXIMUM RATINGS (See Note)

Rating	Symbol	Value		Unit
Power Supply Voltage Relative to VSS	VCC	± 0.5 to +	7.0	V
Voltage Relative to VSS for Any Pin	Vin, Vout	± 0.5 to VCC + 0.5		V
Except VCC
Output Current (per I/O)	Iout	± 20		mA
Power Dissipation	PD	1.0		W
Temperature Under Bias	Tbias	± 10 to +	85	°C
Ambient Temperature	TA	0 to + 70		°C
Storage Temperature Ð Plastic	Tstg	± 55 to + 150		°C

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERAT-

ING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.

This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to these high impedance circuits.

This CMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow of at least 500 linear feet per minute is maintained.

DC OPERATING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted)

RECOMMENDED OPERATING CONDITIONS

Parameter	Symbol	Min	Typ	Max	Unit
Supply Voltage (Operating Voltage Range)	VCC	4.5	5.0	5.5	V
Input High Voltage	VIH	2.2	Ð	VCC + 0.3**	V
Input Low Voltage	VIL	± 0.5*	Ð	0.8	V

*VIL (min) = ± 0.5 V dc; VIL (min) = ± 2.0 V ac (pulse width ≤ 2.0 ns).

**VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width ≤ 2.0 ns).

DC CHARACTERISTICS

		Parameter	Symbol	Min	Max	Unit
Input Leakage Current (All Inputs, Vin = 0 to VCC)			Ilkg(I)	Ð	± 1.0	μA
Output Leakage Current (E = VIH, Vout = 0 to VCC)			Ilkg(O)	Ð	± 1.0	μA
Output Low Voltage (IOL = + 8.0 mA)			VOL	Ð	0.4	V
Output High Voltage (IOH = ± 4.0 mA)			VOH	2.4	Ð	V

POWER SUPPLY CURRENTS

Parameter		Symbol	Min	Typ	Max	Unit
AC Active Supply Current (Iout = 0 mA,	MCM6246±17: tAVAV = 17 ns	ICC	Ð	Ð	205	mA
VCC = max)	MCM6246±20: tAVAV = 20 ns		Ð	185	200
	MCM6246±25: tAVAV = 25 ns		Ð	170	185
	MCM6246±35: tAVAV = 35 ns		Ð	155	170
AC Standby Current (VCC = max,	MCM6246±17: tAVAV = 17 ns	ISB1	Ð	55	60	mA
E = VIH, No other restrictions on	MCM6246±20: tAVAV = 20 ns		Ð	55	60
other inputs)	MCM6246±25: tAVAV = 25 ns		Ð	45	50
	MCM6246±35: tAVAV = 35 ns		Ð	35	40
CMOS Standby Current (E ≥ VCC ± 0.2 V, Vin ≤ VSS + 0.2 V or		ISB2	Ð	10	15	mA
≥ VCC ± 0.2 V) (VCC = max, f = 0 MHz)

MCM6246	MOTOROLA FAST SRAM
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CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested)

	Parameter			Symbol	Typ	Max	Unit
Input Capacitance	All Inputs Except Clocks and	DQs		Cin	4	6	pF
	E, G, W			Cck	5	8
Input/Output Capacitance		DQ		CI/O	5	8	pF

AC OPERATING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted)

Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	0 to 3.0	V	Output Timing Measurement Reference Level . . . . . . .	. . . . . . 1.5 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 2 ns		Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	See Figure 1
Input Timing Measurement Reference Level . . . . . . . . . . . .	. . . 1.5	V

READ CYCLE TIMING (See Note 1)

		MCM6246±17		MCM6246±20		MCM6246±25		MCM6246±35
Parameter	Symbol	Min	Max	Min	Max	Min	Max	Min	Max	Unit	Notes
Read Cycle Time	tAVAV	17	Ð	20	Ð	25	Ð	35	Ð	ns	2, 3
Address Access Time	tAVQV	Ð	17	Ð	20	Ð	25	Ð	35	ns
Enable Access Time	tELQV	Ð	17	Ð	20	Ð	25	Ð	35	ns	4
Output Enable Access Time	tGLQV	Ð	6	Ð	6	Ð	8	Ð	10	ns
Output Hold from Address	tAXQX	5	Ð	5	Ð	5	Ð	5	Ð	ns
Change
Enable Low to Output Active	tELQX	5	Ð	5	Ð	5	Ð	5	Ð	ns	5, 6, 7
Output Enable Low to Output	tGLQX	0	Ð	0	Ð	0	Ð	0	Ð	ns	5, 6, 7
Active
Enable High to Output High±Z	tEHQZ	Ð	8	Ð	8	Ð	10	Ð	12	ns	5, 6, 7
Output Enable High to Output	tGHQZ	Ð	8	Ð	8	Ð	10	Ð	12	ns	5, 6, 7
High±Z
Power Up Time	tELICCH	0	Ð	0	Ð	0	Ð	0	Ð	ns
Power Down Time	tEHICCL	Ð	17	Ð	20	Ð	25	Ð	35	ns
NOTES:

1.W is high for read cycle.

2.Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles.

3.All read cycle timings are referenced from the last valid address to the first transitioning address.

4.Addresses valid prior to or coincident with E going low/E going high.

5.At any given voltage and temperature, tEHQZ max t tELQX min, and tGHQZ max t tGLQX min, both for a given device and from device to device.

6.Transition is measured ± 500 mV from steady±state voltage.

7.This parameter is sampled and not 100% tested.

8.Device is continuously selected (E ≤ VIL, G ≤ VIL).

RL = 50 Ω

OUTPUT

Z0 = 50 Ω

VL = 1.5 V

TIMING LIMITS

The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the system must supply at least that much time. On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never provides data later than that time.

Figure 1. AC Test Load

MOTOROLA FAST SRAM	MCM6246
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