Motorola MCM6926AWJ8R, MCM6926AWJ12R, MCM6926AWJ8, MCM6926AWJ10R, MCM6926AWJ12 Datasheet

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Order this document by MCM6926A/D

Advance Information

128K x 8 Bit Fast Static Random

Access Memory

The MCM6926A is a 1,048,576 bit static random access memory organized as 131,072 words of 8 bits. Static design eliminates the need for external clocks or timing strobes.

Output enable (G) is a special control feature that provides increased system flexibility and eliminates bus contention problems.

This device meets JEDEC standards for functionality and revolutionary pinout, and is available in a 400 mil plastic small±outline J±leaded package.

•Single 3.3 V Power Supply

•Fully Static Ð No Clock or Timing Strobes Necessary

•All Inputs and Outputs Are TTL Compatible

•Three State Outputs

•Fast Access Times: 8, 10, 12, 15 ns

•Center Power and I/O Pins for Reduced Noise

•Fully 3.3 V BiCMOS

BLOCK DIAGRAM

A
A		VDD
		VSS
A
A		MEMORY
	ROW
A		MATRIX
A	DECODER	512 ROWS x 256 x 8
		COLUMNS
A
A
A

DQ			COLUMN I/O
INPUT		COLUMN DECODER
DATA
CONTROL
DQ	A	A	A	A	A	A	A
A
E
W
G

MCM6926A

WJ PACKAGE 400 MIL SOJ CASE 857A±02

PIN ASSIGNMENT

		A			1	32		A
		A			2	31		A
	A				3	30		A
		A			4	29	A
							G
		E			5	28
DQ					6	27		DQ
DQ					7	26	DQ
VDD					8	25		VSS
VSS					9	24	VDD
DQ					10	23	DQ
DQ					11	22		DQ
	W				12	21	A
		A			13	20	A
		A			14	19	A
		A			15	18	A
	A				16	17		A

PIN NAMES

A . . . . . . . . . . . . . . . . . . . . . . . Address Input

E . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable

W . . . . . . . . . . . . . . . . . . . . . . . Write Enable

G . . . . . . . . . . . . . . . . . . . . . Output Enable

DQ . . . . . . . . . . . . . . . . . Data Input/Output

VDD . . . . . . . . . . . . . + 3.3 V Power Supply

VSS . . . . . . . . . . . . . . . . . . . . . . . . . Ground

This document contains information on a new product. Motorola reserves the right to change or discontinue this product without notice.

REV 1 2/25/97

MOTOROLA FAST SRAM	MCM6926A
Motorola, Inc. 1997
	1

TRUTH TABLE (X = Don't Care)

E	G	W	Mode	VDD Current	Output	Cycle
H	X	X	Not Selected	ISB1, ISB2	High±Z	Ð
L	H	H	Output Disabled	IDDA	High±Z	Ð
L	L	H	Read	IDDA	Dout	Read Cycle
L	X	L	Write	IDDA	High±Z	Write Cycle

ABSOLUTE MAXIMUM RATINGS (See Note)

Rating	Symbol	Value		Unit
Power Supply Voltage	VDD	± 0.5 to +	4.6	V
Voltage Relative to VSS for Any Pin	Vin, Vout	± 0.5 to VDD + 0.5		V
Except VDD
Output Current	Iout	± 30		mA
Power Dissipation	PD	0.6		W
Temperature Under Bias	Tbias	± 10 to +	85	°C
Operating Temperature	TA	0 to + 70		°C
Storage Temperature Ð Plastic	Tstg	± 55 to + 125		°C

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.

This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to these high±impedance circuits.

This BiCMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow of at least 500 linear feet per minute is maintained.

DC OPERATING CONDITIONS AND CHARACTERISTICS

(VDD = 3.3 V + 10%, ± 5%, TA = 0 to 70°C, Unless Otherwise Noted)

RECOMMENDED OPERATING CONDITIONS

Parameter	Symbol	Min	Typ	Max	Unit
Supply Voltage (Operating Voltage Range)	VDD	3.135	3.3	3.6	V
Input High Voltage	VIH	2.2	Ð	VDD + 0.3**	V
Input Low Voltage	VIL	± 0.5*	Ð	0.8	V

*VIL (min) = ± 0.5 V dc; VIL (min) = ± 2.0 V ac (pulse width ≤ 2.0 ns) for I ≤ 20.0 mA.

**VIH (max) = VDD + 0.3 V dc; VIH (max) = VDD + 2 V ac (pulse width ≤ 2.0 ns) for I ≤ 20.0 mA.

DC CHARACTERISTICS

		Parameter	Symbol	Min	Max	Unit
Input Leakage Current (All Inputs, Vin = 0 to VDD)			Ilkg(I)	Ð	± 1.0	μA
Output Leakage Current (E = VIH, Vout = 0 to VDD)			Ilkg(O)	Ð	± 1.0	μA
Output Low Voltage (IOL = + 8.0 mA)			VOL	Ð	0.4	V
Output High Voltage (IOH = ± 4.0 mA)			VOH	2.4	Ð	V

MCM6926A	MOTOROLA FAST SRAM
2

POWER SUPPLY CURRENTS (See Note 1)

6926A±8

6926A±10

6926A±12

6926A±15

Parameter

Symbol

Unit

Notes

Typ

Max

Typ

Max

Typ

Max

Typ

Max

AC Active Supply Current

IDDA

Ð

150

Ð

130

Ð

120

Ð

110

mA

2, 3, 4

(Iout = 0 mA) (VDD = max, f = fmax)

Active Quiescent Current

IDD2

Ð

80

Ð

80

Ð

80

Ð

80

mA

(E = VIL, VDD = max, f = 0 MHz)

AC Standby Current

ISB1

Ð

50

Ð

45

Ð

40

Ð

35

mA

2, 3, 4

(E = VIH, VDD = max, f = fmax)

CMOS Standby Current

ISB2

Ð

20

Ð

20

Ð

20

Ð

20

mA

(VDD = max, f = 0 MHz,

E ≥ VDD ± 0.2 V,

Vin ≤ VSS + 0.2 V, or ≥

VDD ± 0.2 V)

NOTES:

1.Typical current = 25°C @ 3.3 V.

2.Reference AC Operating Conditions and Characteristics for input and timing (VIH/VIL, tr/tf, pulse level 0 to 3.0 V, VIH = 3.0 V).

3.All address transition simultaneously low (LSB) and then high (MSB).

4.Data states are all zero.

CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested)

Parameter	Symbol	Typ	Max	Unit
Address Input Capacitance	Cin	Ð	6	pF
Control Pin Input Capacitance	Cin	Ð	6	pF
Input/Output Capacitance	CI/O	Ð	8	pF

MOTOROLA FAST SRAM	MCM6926A
	3