Motorola MCM63P631ATQ75, MCM63P631ATQ75R, MCM63P631ATQ66R, MCM63P631ATQ100R, MCM63P631ATQ117 Datasheet

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

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64K x 32 Bit Pipelined BurstRAM

Synchronous Fast Static RAM

The MCM63P631A is a 2M bit synchronous fast static RAM designed to provide a burstable, high performance, secondary cache for the 68K Family, PowerPC , and Pentium microprocessors. It is organized as 64K words of 32 bits each. This device integrates input registers, an output register, a 2±bit address counter, and high speed SRAM onto a single monolithic circuit for reduced parts count in cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K). CMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability.

Addresses (SA), data inputs (DQx), and all control signals except output enable (G), sleep mode (ZZ), and Linear Burst Order (LBO) are clock (K) controlled through positive±edge±triggered noninverting registers.

Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst addresses can be generated internally by the MCM63P631A (burst sequence operates in linear or interleaved mode dependent upon state of LBO) and controlled by the burst address advance (ADV) input pin.

Write cycles are internally self±timed and are initiated by the rising edge of the clock (K) input. This feature eliminates complex off±chip write pulse generation and provides increased timing flexibility for incoming signals.

Synchronous byte write (SBx), synchronous global write (SGW), and synchronous write enable SW are provided to allow writes to either individual bytes or to all bytes. The four bytes are designated as ªaº, ªbº, ªcº, and ªdº.controlsSBa DQa, SBb controls DQb, etc. Individual bytes are written if the selected byte writes SBx are asserted with SW. All bytes are written if either SGW is asserted or if all SBx and SW are asserted.

For read cycles, pipelined SRAMs output data is temporarily stored by an edge±triggered output register and then released to the output buffers at the next rising edge of clock (K).

The MCM63P631A operates from a 3.3 V power supply, all inputs and outputs are LVTTL compatible.

•MCM63P631A±117 = 4.5 ns access / 8.5 ns cycle (117 MHz) MCM63P631A±100 = 4.5 ns access / 10 ns cycle (100 MHz) MCM63P631A±75 = 7 ns access / 13.3 ns cycle (75 MHz)

MCM63P631A±66 = 8 ns access / 15 ns cycle (66 MHz)

•Single 3.3 V + 10%, ± 5% Power Supply

•ADSP, ADSC, and ADV Burst Control Pins

•Selectable Burst Sequencing Order (Linear/Interleaved)

•Internally Self±Timed Write Cycle

•Byte Write and Global Write Control

•Sleep Mode (ZZ)

•PB1 Version 2.0 Compatible

•Single±Cycle Deselect Timing

•JEDEC Standard 100±Pin TQFP Package

The PowerPC name is a trademark of IBM Corp., used under license therefrom. Pentium is a trademark of Intel Corp.

MCM63P631A

TQ PACKAGE

TQFP

CASE 983A±01

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.

9/30/97

MOTOROLA FAST SRAM	MCM63P631A
Motorola, Inc. 1997
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	FUNCTIONAL BLOCK DIAGRAM
LBO
ADV
K		BURST	2	16
ADSC	K2	COUNTER
		CLR
ADSP
		2
SA	ADDRESS	16	14
SA1
SA0	REGISTER
SGW
SW	WRITE
	REGISTER
SBa	a
	WRITE
	REGISTER
SBb	b
				4
	WRITE
	REGISTER			K
	c
SBc
	WRITE
	REGISTER
SBd	d
	K2	K
SE1	ENABLE	ENABLE
SE2	REGISTER	REGISTER
SE3

64K x 32 ARRAY

32 32

DATA±IN DATA±OUT

REGISTER REGISTER

G

DQa ± DQd

ZZ

MCM63P631A	MOTOROLA FAST SRAM
2

PIN ASSIGNMENT

SA SA SE1 SE2

SBd SBc SBb SBa

SE3

V

V K

SGW SW G

ADSC

ADSP ADV SA SA

DD

SS

NC		100 99 98							97 96				95 94 93 92 91 90 89														88 87 86 85 84 83 82 81
		1																																	80			NC
DQc
		2																																	79			DQb
DQc
		3																																	78			DQb
VDD		4																																	77			VDD
VSS		5
																																			76			VSS
DQc		6
																																			75			DQb
DQc
		7																																	74			DQb
DQc
		8																																	73			DQb
DQc		9																																	72			DQb
VSS		10
																																			71			VSS
VDD		11																																	70			VDD
DQc		12
																																			69			DQb
DQc		13
																																			68			DQb
		14
NC																																			67			VSS
VDD		15																																	66			NC
		16																																				VDD
NC																																			65
VSS
		17																																	64			ZZ
DQd		18																																	63			DQa
DQd		19																																	62			DQa
VDD		20
																																			61			V
VSS		21																																	60			DD
																																						V
DQd		22																																	59			SS
																																						DQa
DQd		23																																	58			DQa
DQd		24
																																			57			DQa
DQd		25																																	56			DQa
VSS		26																																	55			VSS
VDD		27																																	54			VDD
DQd		28																																	53			DQa
		29
DQd																																			52			DQa
NC		30							34 35 36 37 38 39 40 41 42 43 44																				45 46 47 48 49						51			NC
		31			32 33																														50
			LBO		SA SA				SA SA				SA1 SA0 NC NC V										V NC				NC SA		SA SA SA SA SA						NC
																					SS		DD

MOTOROLA FAST SRAM	MCM63P631A
	3

PIN DESCRIPTIONS

Pin Locations

Symbol

Type

Description

85

Input

Synchronous Address Status Controller: Active low, is used to latch a

ADSC

new external address. Used to initiate a READ, WRITE or chip

deselect.

84

Input

Synchronous Address Status Processor: Initiates READ or chip

ADSP

deselect cycle (exception Ð chip deselect does not occur when

ADSP

is asserted and

SE1

is high).

83

Input

Synchronous Address Advance: Increments address count in

ADV

accordance with counter type selected (linear/interleaved).

(a) 52, 53, 56, 57, 58, 59, 62, 63

DQx

I/O

Synchronous Data I/O: ªxº refers to the byte being read or written

(b) 68, 69, 72, 73, 74, 75, 78, 79

(byte a, b, c, d).

(c) 2, 3, 6, 7, 8, 9, 12, 13

(d) 18, 19, 22, 23, 24, 25, 28, 29

86

Input

Asynchronous Output Enable.

G

89

K

Input

Clock: This signal registers the address, data in, and all control signals

except

G, LBO, and ZZ.

31

Input

Linear Burst Order Input: This pin must remain in steady state (this

LBO

signal not registered or latched). It must be tied high or low.

Low Ð linear burst counter (68K/PowerPC).

High Ð interleaved burst counter (486/i960/Pentium).

32, 33, 34, 35, 44, 45, 46,

SA

Input

Synchronous Address Inputs: These inputs are registered and must

47, 48, 49, 81, 82, 99, 100

meet setup and hold times.

36, 37

SA1, SA0

Input

Synchronous Address Inputs: These pins must be wired to the two

LSBs of the address bus for proper burst operation. These inputs are

registered and must meet setup and hold times.

93, 94, 95, 96

Input

Synchronous Byte Write Inputs: ªxº refers to the byte being written (byte

SBx

(a) (b) (c) (d)

a, b, c, d).

SGW

overrides

SBx.

98

Input

Synchronous Chip Enable: Active low to enable chip.

SE1

Negated high Ð blocks

ADSP

or deselects chip when

ADSC

is

asserted.

97

SE2

Input

Synchronous Chip Enable: Active high for depth expansion.

92

Input

Synchronous Chip Enable: Active low for depth expansion.

SE3

88

Input

Synchronous Global Write: This signal writes all bytes regardless of the

SGW

status of the

SBx

and

SW

signals. If only byte write signals

SBx

are

being used, tie this pin high.

87

Input

Synchronous Write: This signal writes only those bytes that have been

SW

selected using the byte write

SBx

pins. If only byte write signals

SBx

are being used, tie this pin low.

64

ZZ

Input

Sleep Mode: This active high asynchronous signal places the RAM into

the lowest power mode. The ZZ pin disables the RAMs internal clock

when placed in this mode. When ZZ is negated, the RAM remains in

low power mode until it is commanded to READ or WRITE. Data

integrity is maintained upon returning to normal operation.

4, 11, 15, 20, 27, 41,

VDD

Supply

Power Supply: 3.3 V + 10%, ± 5%.

54, 61, 65, 70, 77, 91

5, 10, 17, 21, 26, 40,

VSS

Supply

Ground.

55, 60, 67, 71, 76, 90

1, 14, 16, 30, 38, 39,

NC

Ð

No Connection: There is no connection to the chip.

42, 43, 50, 51, 66, 80

MCM63P631A	MOTOROLA FAST SRAM
4

TRUTH TABLE (See Notes 1 through 5)

Address

3

Write 2, 4

Next Cycle

Used

SE2

DQx

SE1

SE3

ADSP

ADSC

ADV

G

Deselect

None

1

X

X

X

0

X

X

High±Z

X

Deselect

None

0

X

1

0

X

X

X

High±Z

X

Deselect

None

0

0

X

0

X

X

X

High±Z

X

Deselect

None

X

X

1

1

0

X

X

High±Z

X

Deselect

None

X

0

X

1

0

X

X

High±Z

X

Begin Read

External

0

1

0

0

X

X

X

High±Z

READ5

Begin Read

External

0

1

0

1

0

X

X

High±Z

READ5

Continue Read

Next

X

X

X

1

1

0

1

High±Z

READ

Continue Read

Next

X

X

X

1

1

0

0

DQ

READ

Continue Read

Next

1

X

X

X

1

0

1

High±Z

READ

Continue Read

Next

1

X

X

X

1

0

0

DQ

READ

Suspend Read

Current

X

X

X

1

1

1

1

High±Z

READ

Suspend Read

Current

X

X

X

1

1

1

0

DQ

READ

Suspend Read

Current

1

X

X

X

1

1

1

High±Z

READ

Suspend Read

Current

1

X

X

X

1

1

0

DQ

READ

Begin Write

External

0

1

0

1

0

X

X

High±Z

WRITE

Continue Write

Next

X

X

X

1

1

0

X

High±Z

WRITE

Continue Write

Next

1

X

X

X

1

0

X

High±Z

WRITE

Suspend Write

Current

X

X

X

1

1

1

X

High±Z

WRITE

Suspend Write

Current

1

X

X

X

1

1

X

High±Z

WRITE

NOTES:

1.X = Don't Care. 1 = logic high. 0 = logic low.

2.Write is defined as either 1) any SBx and SW low or 2) SGW is low.

3.G is an asynchronous signal and is not sampled by the clock K. G drives the bus immediately (tGLQX) following G going low.

4.On write cycles that follow read cycles, G must be negated prior to the start of the write cycle to ensure proper write data setup times. G must also remain negated at the completion of the write cycle to ensure proper write data hold times.

5.This READ assumes the RAM was previously deselected.

MOTOROLA FAST SRAM	MCM63P631A
	5