Motorola MCM6227AWJ45, MCM6227AWJ45R2, MCM6227AWJ20R2, MCM6227AWJ25, MCM6227AWJ25R2 Datasheet

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Order this document by MCM6227A/D

1M x 1 Bit Static Random

Access Memory

The MCM6227A is a 1,048,576 bit static random±access memory organized as 1,048,576 words of 1 bit, fabricated using high±performance silicon±gate CMOS technology. Static design eliminates the need for external clocks or timing strobes while CMOS circuitry reduces power consumption and provides for greater reliability.

The MCM6227A is equipped with a chip enable (E) pin. In less than a cycle time after E goes high, the part enters a low±power standby mode, remaining in that state until E goes low again.

The MCM6227A is available in 400 mil, 28±lead surface±mount SOJ packages.

•Single 5 V ± 10% Power Supply

•Fast Access Times: 20, 25, 35, and 45 ns

•Equal Address and Chip Enable Access Times

•Input and Output are TTL Compatible

•Three±State Output

•Low Power Operation: 160/140/130/120 mA Maximum, Active AC

		BLOCK DIAGRAM
A0
A1									VCC
										VSS
A2
A3
A4	ROW		MEMORY MATRIX
				1024 ROWS x
	DECODER
A5			1024 COLUMNS
A6
A7
A8
A9
D	INPUT				COLUMN I/O					Q
	DATA
	CONTROL			COLUMN DECODER
E
	A10	A11	A12	A13	A14	A15	A16	A17	A18	A19
W

MCM6227A

PACKAGE

400 MIL SOJ CASE 810±03

PIN ASSIGNMENT

A0				1	28			VCC
A1				2	27			A19
A2				3	26			A18
A3				4	25			A17
A4				5	24			A16
A5				6	23			A15
NC				7	22			A14
A6				8	21			NC
A7				9	20			A13
A8				10	19			A12
A9				11	18			A11
	Q			12	17			A10
				13	16			D
	W
VSS				14	15
								E

PIN NAMES

A0 ± A19 . . . . . . . . . . . . . Address Inputs

W . . . . . . . . . . . . . . . . . . . . . Write Enable

E . . . . . . . . . . . . . . . . . . . . . . Chip Enable

D . . . . . . . . . . . . . . . . . . . . . . . . Data Input

Q . . . . . . . . . . . . . . . . . . . . . Data Output

NC . . . . . . . . . . . . . . . . . . No Connection

VCC . . . . . . . . . . . . . + 5 V Power Supply

VSS . . . . . . . . . . . . . . . . . . . . . . . . Ground

REV 4 5/95

Motorola, Inc. 1994

MCM6227A TRUTH TABLE

	E			W		Mode	I/O Pin	Cycle	Current
H				X		Not Selected	High±Z	Ð	ISB1, ISB2
	L			H		Read	Dout	Read	ICCA
	L			L		Write	High±Z	Write	ICCA

H = High, L = Low, X = Don't Care

ABSOLUTE MAXIMUM RATINGS (See Note)

Rating	Symbol	Value	Unit
Power Supply Voltage Relative to VSS	VCC	± 0.5 to 7.0	V
Voltage Relative to VSS for Any Pin	Vin, Vout	± 0.5 to VCC + 0.5	V
Except VCC
Output Current	Iout	± 20	mA
Power Dissipation	PD	1.1	W
Temperature Under Bias	Tbias	± 10 to + 85	°C
Operating Temperature	TA	0 to + 70	°C
Storage Temperature	Tstg	± 55 to + 150	°C

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.

This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to these high±impedance circuits.

This CMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow of at least 500 linear feet per minute is maintained.

DC OPERATING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 V ± 10%, TA = 0 to 70°C, Unless Otherwise Noted)

RECOMMENDED OPERATING CONDITIONS

Parameter	Symbol	Min	Max	Unit
Supply Voltage (Operating Voltage Range)	VCC	4.5	5.5	V
Input High Voltage	VIH	2.2	VCC + 0.3**	V
Input Low Voltage	VIL	± 0.5*	0.8	V

*VIL (min) = ± 0.5 V dc; VIL (min) = ± 2.0 V ac (pulse width ≤ 20 ns).

**VIH (max) = VCC = 0.3 V dc; VIH (max) = VCC + 2 V ac (pulse width ≤ 20 ns).

DC CHARACTERISTICS AND SUPPLY CURRENTS

					Parameter		Symbol	Min	Typ*	Max	Unit
Input Leakage Current (All Inputs, Vin = 0 to VCC)							Ilkg(I)	Ð	Ð	± 1	μA
				= VIH, Vout = 0 to VCC)			Ilkg(O)			± 1	μA
Output Leakage Current (E								Ð	Ð
AC Active Supply Current (Iout = 0 mA, VCC = max)							ICCA				mA
						MCM6227A±20: tAVAV = 20 ns		Ð	120	160
						MCM6227A±25: tAVAV = 25 ns		Ð	110	140
						MCM6227A±35: tAVAV = 35 ns		Ð	100	130
						MCM6227A±45: tAVAV = 45 ns		Ð	90	120
AC Standby Current (VCC = max,						= VIH, f = fmax)	ISB1	Ð	7	20	mA
					E
			≥ VCC ± 0.2 V, Vin ≤ VSS + 0.2 V				ISB2	Ð	4	15	mA
CMOS Standby Current (E
or ≥ VCC ± 0.2 V, VCC = max, f = 0 MHz)
Output Low Voltage (IOL = + 8.0 mA)							VOL	Ð	Ð	0.4	V
Output High Voltage (IOH = ± 4.0 mA)							VOH	2.4	Ð	Ð	V
* Typical values are measured at 25°C, VCC = 5 V.

MCM6227A	MOTOROLA FAST SRAM
2

CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested)

	Characteristic					Symbol	Typ	Max	Unit
Input Capacitance	All Inputs Except Clocks and D, Q					Cin	4	6	pF
		E	and	W			5	8
Input and Output Capacitance			D, Q			Cin, Cout	5	8	pF

AC OPERATING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted)

Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	0 to 3.0	V	Output Timing Measurement Reference Level . . . . . .	. . . . . . . 1.5 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 2 ns		Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	See Figure 1A
Input Timing Measurement Reference Level . . . . . . . . . . . .	. . . 1.5	V

READ CYCLE TIMING (See Notes 1 and 2)

		6227A±20		6227A±25		6227A±35		6227A±45
Parameter	Symbol	Min	Max	Min	Max	Min	Max	Min	Max	Unit	Notes
Read Cycle Time	tAVAV	20	Ð	25	Ð	35	Ð	45	Ð	ns	2,3
Address Access Time	tAVQV	Ð	20	Ð	25	Ð	35	Ð	45	ns
Enable Access Time	tELQV	Ð	20	Ð	25	Ð	35	Ð	45	ns	4
Output Hold from Address Change	tAXQX	5	Ð	5	Ð	5	Ð	5	Ð	ns
Enable Low to Output Active	tELQX	5	Ð	5	Ð	5	Ð	5	Ð	ns	5, 6, 7
Enable High to Output High±Z	tEHQZ	0	9	0	10	0	12	Ð	18	ns	5, 6, 7
Power Up Time	tELICCH	0	Ð	0	Ð	0	Ð	0	Ð	ns
Power Down Time	tEHICCL	Ð	20	Ð	25	Ð	35	Ð	45	ns
NOTES:

1.W is high for read cycle.

2.Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles.

3.All timings are referenced from the last valid address to the first transitioning address.

4.Addresses valid prior to or coincident with E going low.

5.At any given voltage and temperature, tEHQZ max is less than tELQX min, both for a given device and from device to device.

6.Transition is measured ± 500 mV from steady±state voltage with load of Figure 1B.

7.This parameter is sampled and not 100% tested.

8.Device is continuously selected (E ≤ VIL).

	AC TEST LOADS
			+ 5 V
OUTPUT	RL = 50 Ω		480 Ω
	OUTPUT
Z0	= 50 Ω	Ω	5 pF
	255
	VL = 1.5 V

Figure 1A

Figure 1B

TIMING LIMITS

The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the system must supply at least that much time (even though most devices do not require it). On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never provides data later than that time.

MOTOROLA FAST SRAM	MCM6227A
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