Motorola MCM69F618CTQ10R, MCM69F618CTQ12, MCM69F618CTQ8.5R, MCM69F618CTQ9, MCM69F618CTQ10 Datasheet

MCM69F618C

1

MOTOROLA FAST SRAM

64K x 18 Bit Flow–Through

BurstRAM Synchronous

Fast Static RAM

The MCM69F618C is a 1M–bit synchronous fast static RAM designed to pro-

vide a burstable, high performance, secondary cache for the 68K Family,

PowerPC, 486, i960, and Pentium microprocessors. It is organized as 64K

words of 18 bits each. This device integrates input registers, a 2–bit address

counter, and high speed SRAM onto a single monolithic circuit for reduced parts

count in cache data RAM applications. Synchronous design allows precise cycle

control with the use of an external clock (K). BiCMOS circuitry reduces the overall

power consumption of the integrated functions for greater reliability .

Addresses (SA), data inputs (DQx), and all control signals except output

enable (G

) and Linear Burst Order (LBO) are clock (K) controlled through

positive–edge–triggered noninverting registers.

Bursts can be initiated with either ADSP

or ADSC input pins. Subsequent burst

addresses can be generated internally by the MCM69F618C (burst sequence

operates in linear or interleaved mode dependent upon the state of LBO

) and

controlled by the burst address advance (ADV

) input pin.

Write cycles are internally self–timed and initiated by the rising edge of the

clock (K) input. This feature eliminates complex off–chip write pulse generation

and provides increased timing flexibility for incoming signals.

Synchronous byte write (SBx

), synchronous global write (SGW), and syn-

chronous write enable SW

are provided to allow writes to either individual bytes

or to both bytes. The two bytes are designated as “a” and “b”. SBa

controls DQa

and SBb

controls DQb. Individual bytes are written if the selected byte writes SBx

are asserted with SW. Both bytes are written if either SGW is asserted or if all SBx

and SW are asserted.

For read cycles, a flow–through SRAM allows output data to simply flow freely

from the memory array .

The MCM69F618C operates from a 3.3 V power supply and all inputs and

outputs are L VTTL compatible and 5 V tolerant.

• MCM69F618C–8.5 = 8.5 ns Access / 12 ns Cycle

MCM69F618C–9 = 9 ns Access / 12 ns Cycle

MCM69F618C–10 = 10 ns Access / 15 ns Cycle

MCM69F618C–12= 12 ns Access / 16.6 ns Cycle

• Single 3.3 V + 10%, – 5% Power Supply

• ADSP

, ADSC, and ADV Burst Control Pins

• Selectable Burst Sequencing Order (Linear/Interleaved)

• Internally Self–Timed Write Cycle

• Byte Write and Global Write Control

• 5 V Tolerant on all Pins (Inputs and I/Os)

• 100–Pin TQFP Package

The PowerPC name is a trademark of IBM Corp., used under license therefrom.

i960 and Pentium are trademarks of Intel Corp.

Order this document

by MCM69F618C/D

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

MCM69F618C

TQ PACKAGE

TQFP

CASE 983A–01

REV 2

2/18/98

 Motorola, Inc. 1998

MCM69F618C

2

MOTOROLA FAST SRAM

FUNCTIONAL BLOCK DIAGRAM

WRITE

REGISTER

a

WRITE

REGISTER

b

ENABLE

REGISTER

BURST

COUNTER

ADSP

G

CLR

SBa

SBb

SE3

14

16

SGW

K2

ADDRESS

REGISTER

16

DATA–IN

REGISTER

64K x 18 ARRAY

SE2

LBO

ADV

K

ADSC

SA

SA1

SA0

SW

SE1

K

2

18 18

2

2

K2

DQa, DQb

FUNCTIONAL BLOCK DIAGRAM

MCM69F618C

3

MOTOROLA FAST SRAM

PIN ASSIGNMENT

71

72

NC

V

DD

SA

69

70

66

67

68

64

65

61

62

63

37 3834 35 36 42 4339 40 41 45 4644

60

59

58

57

56

55

54

53

52

51

31 32 33

74

75

76

77

78

79

80

50494847

NC

NC

V

SS

DQa

NC

DQa

DQa

V

SS

V

DD

DQa

DQa

V

DD

V

SS

V

SS

V

DD

NC

NC

NC

DQb

DQb

DQb

DQb

NC

SA

SA

SE1

NC

K

NC

ADV

G

ADSC

ADSP

SA0

SA

SA

SA

SA

NC

NC

NC

NC

V

SS

LBO

SA1

V

DD

V

DD

NC

DQa

V

SS

DQa

DQa

NC

DQa

V

SS

V

DD

NC

NC

V

SS

V

DD

NC

NC

DQb

V

DD

V

SS

V

SS

V

DD

DQb

DQb

DQb

DQb

NC

73

NC

94 9397 96 95 89 8892 91 90 86 8587100 99 98 81828384

10

9

12

11

15

14

13

17

16

20

19

18

21

22

23

24

25

26

27

28

29

30

7

6

5

4

3

2

1

8

SA

SA

SW

SE2

SBb

SBa

SE3

V

SS

V

DD

SGW

NC

NC

V

DD

V

SS

NC

NC

NC

NC

NC

SA

SA

SA

SA

SA

MCM69F618C

4

MOTOROLA FAST SRAM

PIN DESCRIPTIONS

Pin Locations Symbol

Type Description

85 ADSC Input Synchronous Address Status Controller: Initiates READ, WRITE or chip

deselect cycle.

84 ADSP Input Synchronous Address Status Processor: Initiates READ, WRITE or

chip deselect cycle (exception — chip deselect does not occur when

ADSP

is asserted and SE1 is high).

83 ADV Input Synchronous Address Advance: Increments address count in

accordance with counter type selected (linear/interleaved).

(a) 58, 59, 62, 63, 68, 69, 72, 73, 74

(b) 8, 9, 12, 13, 18, 19, 22, 23, 24

DQx I/O Synchronous Data I/O: “x” refers to the byte being read or written

(byte a, b).

86 G Input Asynchronous Output Enable Input:

Low — enables output buffers (DQx pins).

High — DQx pins are high impedance.

89 K Input Clock: This signal registers the address, data in, and all control signals

except G

and LBO.

31 LBO Input Linear Burst Order Input: This pin must remain in steady state (this

signal not registered or latched). It must be tied high or low.

Low — linear burst counter (68K/PowerPC).

High — interleaved burst counter (486/i960/Pentium).

32, 33, 34, 35, 44, 45, 46,

47, 48, 80, 81, 82, 99, 100

SA Input Synchronous Address Inputs: These inputs are registered and must

meet setup and hold times.

36, 37 SA1,SA0 Input Synchronous Address Inputs: these pins must be wired to the two LSBs

of the address bus for proper burst operation. These inputs are

registered and must meet setup and hold times.

93, 94

(a) (b)

SBx Input Synchronous Byte Write Inputs: “x” refers to the byte being written (byte

a, b). SGW

overrides SBx.

98 SE1 Input Synchronous Chip Enable: Active low to enable chip.

Negated high–blocks ADSP

or deselects chip when ADSC is asserted.

97 SE2 Input Synchronous Chip Enable: Active high for depth expansion.

92 SE3 Input Synchronous Chip Enable: Active low for depth expansion.

88 SGW Input Synchronous Global Write: This signal writes all bytes regardless of the

status of the SBx

and SW signals. If only byte write signals SBx are

being used, tie this pin high.

87 SW Input Synchronous Write: This signal writes only those bytes that have been

selected using the byte write SBx

pins. If only byte write signals SBx

are being used, tie this pin low.

4, 11, 15, 20, 27, 41, 54,

61, 65, 70, 77, 91

V

DD

Supply Power Supply: 3.3 V + 10%, – 5%.

5, 10, 17, 21, 26, 40, 55,

60, 67, 71, 76, 90

V

SS

Supply Ground.

64 NC Input No Connection: There is no connection to the chip. For compatibility

reasons, it is recommended that this pin be tied low for system designs

that do not have a sleep mode associated with the cache/memory

controller. Other vendors’ RAMs may have implemented this Sleep

Mode (ZZ) feature.

1, 2, 3, 6, 7, 14, 16, 25, 28, 29, 30,

38, 39, 42, 43, 49, 50, 51, 52,

53, 56, 57, 66, 75, 78, 79, 95, 96

NC — No Connection: There is no connection to the chip.