Motorola MCM6323AYJ10, MCM6323AYJ10A, MCM6323AYJ10AR, MCM6323AYJ10R, MCM6323ATS15AR Datasheet

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

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MCM6323A

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64K x 16 Bit 3.3 V Asynchronous

Fast Static RAM

The MCM6323A is a 1,048,576 bit static random access memory organized as 65,536 words of 16 bits. Static design eliminates the need for external clocks or timing strobes; CMOS circuitry reduces power consumption and provides for greater reliability.

The MCM6323A is equipped with chip enable (E), write enable (W), and output

enable (G) pins, allowing for greater system flexibility and eliminating bus contention

problems. Separate byte enable controls (LB and UB) allow individual bytes to be written and read. LB controls the 8 DQa bits, while UB controls the 8 DQb bits.

The MCM6323A is available in a 400 mil small±outline J±leaded (SOJ) package and a 44±lead TSOP Type II package in copper leadframe for optimum printed circuit board (PCB) reliability.

•Single 3.3 V ± 0.3 V Power Supply

•Fast Access Time: 10, 12, 15 ns

•Equal Address and Chip Enable Access Time

•All Inputs and Outputs are TTL Compatible

•Data Byte Control

•Fully Static Operation

•Power Operation: 140/135/130 mA Maximum, Active AC

•Industrial Temperature Option: ± 40 to + 85°C Part Number: SCM6323AYJ10A

			BLOCK DIAGRAM
G	OUTPUT				HIGH BYTE OUTPUT ENABLE
	ENABLE
	BUFFER				LOW BYTE OUTPUT ENABLE
			7				8	HIGH	8	DQb
A	ADDRESS							BYTE
16	BUFFERS	9	ROW		COLUMN			OUTPUT		8
			DECODER		DECODER			BUFFER
							8	HIGH	8
E	CHIP							BYTE
								WRITE
	ENABLE
								DRIVER
	BUFFER
							SENSE
			64K x 16			16
							AMPS
			BIT
								LOW
W	WRITE		MEMORY				8		8	DQa
	ENABLE		ARRAY					BYTE
	BUFFER							OUTPUT		8
								BUFFER
							8	LOW	8
								BYTE
LB	BYTE							WRITE
								DRIVER
UB	ENABLE			HIGH BYTE WRITE ENABLE
	BUFFER
				LOW BYTE WRITE ENABLE

This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice.

REV 1 10/17/97

YJ PACKAGE 400 MIL SOJ CASE 919±01

TS PACKAGE 44±LEAD TSOP TYPE II CASE 924A±01

PIN ASSIGNMENT

	A					1	44	A
	A					2	43	A
	A					3	42	A
	A					4	41
									G
	A					5	40
									UB
						6	39
		E							LB
DQa						7	38	DQb
DQa						8	37	DQb
DQa						9	36	DQb
DQa						10	35	DQb
VDD						11	34	VSS
VSS						12	33	VDD
DQa						13	32	DQb
DQa						14	31	DQb
DQa						15	30	DQb
DQa						16	29	DQb
						17	28	NC
	W
	A					18	27	A
	A					19	26	A
		A				20	25	A
		A				21	24	A
NC						22	23	NC

PIN NAMES

A . . . . . . . . . . . . . . . . . . . . . . . . Address Input

E . . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable

W . . . . . . . . . . . . . . . . . . . . . . . . Write Enable

G . . . . . . . . . . . . . . . . . . . . . . Output Enable

UB . . . . . . . . . . . . . . . . . . . . . . . . Upper Byte

LB . . . . . . . . . . . . . . . . . . . . . . . . . Lower Byte

DQa . . . . . . . . . . . . Lower Data Input/Output

DQb . . . . . . . . . . . . Upper Data Input/Output

VDD . . . . . . . . . . . . . . + 3.3 V Power Supply

VSS . . . . . . . . . . . . . . . . . . . . . . . . . . Ground

NC . . . . . . . . . . . . . . . . . . . . . No Connection

MOTOROLA FAST SRAM	MCM6323A
Motorola, Inc. 1997
	1

TRUTH TABLE (X = Don't Care)

E

G

W

LB

UB

Mode

VDD Current

DQa's

DQb's

H

X

X

X

X

Not Selected

ISB1, ISB2

High±Z

High±Z

L

H

H

X

X

Output Disabled

IDDA

High±Z

High±Z

L

X

X

H

H

Output Disabled

IDDA

High±Z

High±Z

L

L

H

L

H

Low Byte Read

IDDA

Dout

High±Z

L

L

H

H

L

High Byte Read

IDDA

High±Z

Dout

L

L

H

L

L

Word Read

IDDA

Dout

Dout

L

X

L

L

H

Low Byte Write

IDDA

Din

High±Z

L

X

L

H

L

High Byte Write

IDDA

High±Z

Din

L

X

L

L

L

Word Write

IDDA

Din

Din

ABSOLUTE MAXIMUM RATINGS (See Notes)

Rating		Symbol	Value		Unit
Supply Voltage		VDD	± 0.5 to +	4.6	V
Voltage on Any Pin		Vin	± 0.5 to VDD + 0.5		V
Output Current per Pin		Iout	± 20		mA
Package Power Dissipation		PD	.75		W
Temperature Under Bias	Commerial	Tbias	± 10 to +	85	°C
	Industrial		± 45 to +	90
Operating Temperature	Commerial	TA	0 to + 70		°C
	Industrial		± 40 to +	85
Storage Temperature		Tstg	± 55 to + 150		°C
NOTES:

1.Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.

2.All voltages are referenced to VSS.

3.Power dissipation capability will be dependent upon package characteristics and use environment.

This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to these high±impedance circuits.

This CMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow of at least 500 linear feet per minute is maintained.

MCM6323A	MOTOROLA FAST SRAM
2

DC OPERATING CONDITIONS AND CHARACTERISTICS

(VDD = 3.3 V ± 0.3 V, TA = 0 to 70°C, Unless Otherwise Noted) (TA = ± 40 to + 85°C for Industrial Temperature Offering)

RECOMMENDED OPERATING CONDITIONS

Parameter	Symbol	Min	Typ	Max	Unit
Power Supply Voltage	VDD	3.0	3.3	3.6	V
Input High Voltage	VIH	2.2	Ð	VDD + 0.3**	V
Input Low Voltage	VIL	± 0.5*	Ð	0.8	V

*VIL (min) = ± 0.5 V dc; VIL (min) = ± 2.0 V ac (pulse width ≤ 20 ns) for I ≤ 20.0 mA.

**VIH (max) = VDD + 0.3 V dc; VIH (max) = VDD + 2.0 V ac (pulse width ≤ 20 ns) for I ≤ 20.0 mA.

DC CHARACTERISTICS

		Parameter		Symbol	Min	Max	Unit
Input Leakage Current (All Inputs, Vin = 0 to VDD)				Ilkg(I)	Ð	± 1.0	μA
		= VIH, Vout = 0 to VDD)		Ilkg(O)		± 1.0	μA
Output Leakage Current (E					Ð
Output Low Voltage			(IOL = + 4.0 mA)	VOL	Ð	0.4	V
			(IOL = + 100 μA)			VSS + 0.2
Output High Voltage			(IOH = ± 4.0 mA)	VOH	2.4	Ð	V
			(IOH = ± 100 μA)		VDD ± 0.2

POWER SUPPLY CURRENTS (See Note 1)

					Parameter		Symbol	6323A±10	6323A±12	6323A±15	Unit	Notes
	AC Active Supply Current (Iout = 0 mA)					Commerical	IDDA	140	135	130	mA	2
	(VDD = max, f = fmax)					Industrial		150	140	135
					= VIH, VDD = max,		ISB1
	AC Standby Current (E					Commerical		40	35	30	mA	2
	f = fmax)					Industrial		45	40	35
	CMOS Standby Current (VDD = max, f = 0 MHz,					Commerical	ISB2	5	5	5	mA
	E	≥	VDD ± 0.2 V, Vin ≤ VSS + 0.2 V,			Industrial		5	5	5
	or ≥		VDD ± 0.2 V)

NOTES:

1.Typical current = 25°C @ 3.3 V.

2.Reference AC Operating Conditions and Characteristics for input and timing (VIH/VIL, tr/tf, pulse level 0 to 3.0 V, VIH = 3.0 V, VIL = 0 V).

CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested)

Parameter	Symbol	Typ	Max	Unit
Address Input Capacitance	Cin	Ð	6	pF
Control Input Capacitance	Cin	Ð	6	pF
Input/Output Capacitance	CI/O	Ð	8	pF

MOTOROLA FAST SRAM	MCM6323A
	3

AC OPERATING CONDITIONS AND CHARACTERISTICS

(VDD = 3.3 V ± 0.3 V, TA = 0 to +70°C, Unless Otherwise Noted) (TA = ± 40 to + 85°C for Industrial Temperature Offering)

Logic Input Timing Measurement Reference Level

. . . . . . . .

1.50 V

Output Timing Reference Level . . . . . .

. . . . . . . . .

. . . . . . . .

.

. 1.50 V

Logic Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . .

. . . . . 0 to 3.0 V

Output Load . . . .

. . . . . . . . .

. . . . . . . . .

. . . . . . . . .

. . . . . See Figure 1

Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . .

.

2 ns

READ CYCLE TIMING (See Notes 1, 2, 3, and 4)

MCM6323A±10

MCM6323A±12

MCM6323A±15

Parameter

Symbol

Unit

Notes

Min

Max

Min

Max

Min

Max

Read Cycle Time

tAVAV

10

Ð

12

Ð

15

Ð

ns

5

Address Access Time

tAVQV

Ð

10

Ð

12

Ð

15

ns

Enable Access Time

tELQV

Ð

10

Ð

12

Ð

15

ns

Output Enable Access Time

tGLQV

Ð

4

Ð

5

Ð

6

ns

6

Output Hold from Address Change

tAXQX

3

Ð

3

Ð

3

Ð

ns

Enable Low to Output Active

tELQX

3

Ð

3

Ð

3

Ð

ns

6, 7, 8

Output Enable Low to Output Active

tGLQX

0

Ð

0

Ð

0

Ð

ns

6, 7, 8

Enable High to Output High±Z

tEHQZ

Ð

4

Ð

5

Ð

6

ns

6, 7, 8

Output Enable High to Output High±Z

tGHQZ

Ð

4

Ð

5

Ð

6

ns

6, 7, 8

Byte Enable Access Time

tBLQV

Ð

4

Ð

5

Ð

6

ns

Byte Enable Low to Output Active

tBLQX

0

Ð

0

Ð

0

Ð

ns

6, 7, 8

Byte High to Output High±Z

tBHQZ

0

5

0

5

0

5

ns

6, 7, 8

NOTES:

1.W is high for read cycle.

2.For common I/O applications, minimization, or elimination of bus contention conditions is necessary during read and write cycles.

3.Device is continuously selected (E = VIL, G = VIL, and LB and/or UB = VIL).

4.Addresses valid prior to or coincident with E going low.

5.All read cycle timings are referenced from the last valid address to the first transitioning address.

6.Transition is measured 200 mV from steady±state voltage.

7.At any given voltage and temperature, tEHQZ (max) < tELQX (min), and tGHQZ (max) < tGLQX (min), both for a given device and from device to device.

8.This parameter is sampled and not 100% tested.

MCM6323A	MOTOROLA FAST SRAM
4