Motorola MCM69P817ZP3R, MCM69P817ZP3, MCM69P817ZP3.5, MCM69P817ZP2.5, MCM69P817ZP3.5R Datasheet

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SEMICONDUCTOR TECHNICAL DATA

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256K x 18 Bit Pipelined

BurstRAM Synchronous

Fast Static RAM

The MCM69P817 is a 4M bit synchronous fast static RAM designed to provide a burstable, high performance, secondary cache for the PowerPC and other high performance microprocessors. It is organized as 256K words of 18 bits each. This device integrates input registers, an output register, a 2±bit address counter, and a high speed SRAM onto a single monolithic circuit for reduced parts count in cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K).

Addresses (SA), data inputs (DQx), and all control signals except output enable (G) and linear burst order (LBO) are clock (K) controlled through positive± edge±triggered noninverting registers.

Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst addresses can be generated internally by the MCM69P817 (burst sequence operates in linear or interleaved mode dependent upon the state of LBO) and controlled by the burst address advance (ADV) input pin.

Write cycles are internally self±timed and are initiated by the rising edge of the clock (K) input. This feature eliminates complex off±chip write pulse generation and provides increased timing flexibility for incoming signals.

Synchronous byte write (SBx), synchronous global write (SGW), and synchronous write enable (SW) are provided to allow writes to either individual bytes or to all bytes. The two bytes are designated as ªaº and ªbº. SBacontrols DQa and SBb controls DQb. Individual bytes are written if the selected byte writes SBx are asserted with SW. All bytes are written if either SGW is asserted or if all SBx and SW are asserted.

For read cycles, pipelined SRAMs output data is temporarily stored by an edge±triggered output register and then released to the output buffers at the next rising edge of clock (K).

The MCM69P817 operates from a 3.3 V core power supply and all outputs operate on a 3.3 V or 2.5 V power supply. All inputs and outputs are JEDEC standard JESD8±5 compatible.

• MCM69P817 Speed Options

		Pipelined
Speed	tKHKH	tKHQV	Setup	Hold	IDD	Pkg
200 MHz	5 ns	2.5 ns	0.5 ns	1 ns	475 mA	PBGA

180 MHz	5.5 ns	3.0 ns	0.5 ns	1 ns	450 mA	PBGA

166 MHz	6 ns	3.5 ns	0.5 ns	1 ns	425 mA	PBGA

•3.3 V + 10%, ± 5% Core Power Supply, Operates with a 3.3 V or 2.5 V I/O Supply

•ADSP, ADSC, and ADV Burst Control Pins

•Selectable Burst Sequencing Order (Linear/Interleaved)

•Single±Cycle Deselect Timing

•Internally Self±Timed Write Cycle

•Byte Write and Global Write Control

•PB1 Version 2.0 Compatible

•JEDEC Standard 119±Pin PBGA Package

BurstRAM is a trademark of Motorola, Inc.

The PowerPC name is a trademark of IBM Corp., used under license therefrom.

MCM69P817

ZP PACKAGE

PBGA

CASE 999±01

This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice.

6/10/97

MOTOROLA FAST SRAM	MCM69P817
Motorola, Inc. 1997
	1

Motorola MCM69P817ZP3R, MCM69P817ZP3, MCM69P817ZP3.5, MCM69P817ZP2.5, MCM69P817ZP3.5R Datasheet

	FUNCTIONAL BLOCK DIAGRAM
LBO
ADV
K		BURST	2	18
		BURST	2	18
ADSC	K2	COUNTER
	K2	CLR
ADSP		CLR
ADSP
		2
SA	ADDRESS	18	16
SA1	ADDRESS	18	16
SA1	REGISTER
SA0	REGISTER
SA0
SGW
SW	WRITE
	REGISTER
SBa	b
SBa
				2
	WRITE
	REGISTER			K
	c			K
SBb	c
SBb
	K2	K
SE1	ENABLE	ENABLE
SE2	ENABLE	ENABLE
SE2	REGISTER	REGISTER
SE3	REGISTER	REGISTER
SE3

256K x 18 ARRAY

18 18

DATA±IN DATA±OUT REGISTER REGISTER

DQa ± DQb

MCM69P817	MOTOROLA FAST SRAM
2

PIN ASSIGNMENT

1	2	3	4	5	6	7
A	SA	SA		SA	SA	VDDQ
VDDQ			ADSP
B	SE2	SA	ADSC	SA	SE3	NC
NC
C	SA	SA	VDD	SA	SA	NC
NC
D		VSS		VSS		NC
DQb	NC		NC		DQa
E		VSS		VSS
NC	DQb		SE1		NC	DQa
F		VSS		VSS	DQa	VDDQ
VDDQ	NC		G
G			ADV	VSS	NC	DQa
NC	DQb	SBb
H		VSS		VSS
DQb	NC		SGW		DQa	NC
J	VDD		VDD		VDD	VDDQ
VDDQ		NC		NC
K		VSS		VSS		DQa
NC	DQb		K		NC
L		VSS	NC
DQb	NC			SBa	DQa	NC
M			SW	VSS		VDDQ
VDDQ	DQb	VSS			NC
N		VSS		VSS		NC
DQb	NC		SA1		DQa
P		VSS		VSS
NC	DQb		SA0		NC	DQa
R	SA	LBO	VDD	NC	SA	NC
NC
T	SA	SA		SA	SA	NC
NC			NC
U	NC	NC	NC	NC	NC	VDDQ
VDDQ

TOP VIEW 119 BUMP PBGA

Not to Scale

MOTOROLA FAST SRAM	MCM69P817
	3

PBGA PIN DESCRIPTIONS

Pin Locations	Symbol	Type		Description

4B	ADSC	Input	Synchronous Address Status Controller: Active low, interrupts any
			ongoing burst and latches a new external address. Used to initiate a
			READ, WRITE, or chip deselect.

4A	ADSP	Input	Synchronous Address Status Processor: Active low, interrupts any
			ongoing burst and latches a new external address used to initiate a new
			READ or chip deselect (exception Ð chip deselect does not occur

			when ADSP is asserted and SE1 is high).

4G	ADV	Input	Synchronous Address Advance: Increments address count in
			accordance with counter type selected (linear/interleaved).

(a) 6D, 7E, 6F, 7G, 6H, 7K, 6L, 6N, 7P	DQx	I/O	Synchronous Data I/O: ªxº refers to the byte being read or written
(b) 1D, 2E, 2G, 1H, 2K, 1L, 2M, 1N, 2P			(byte a, b).

4F	G	Input	Asynchronous Output Enable Input:
			Low Ð enables output buffers (DQx pins).
			High Ð DQx pins are high impedance.

4K	K	Input	Clock: This signal registers the address, data in, and all control signals
			except G and LBO.

3R	LBO	Input	Linear Burst Order Input: This pin must remain in steady state (this
			signal not registered or latched). It must be tied high or low.
			Low Ð linear burst counter (68K/PowerPC).
			High Ð interleaved burst counter (486/i960/Pentium).

2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C,	SA	Input	Synchronous Address Inputs: These inputs are registered and must
5C, 6C, 2R, 6R, 2T, 3T, 5T, 6T			meet setup and hold times.

4N, 4P	SA1, SA0	Input	Synchronous Address Inputs: These pins must be wired to the two
			LSBs of the address bus for proper burst operation. These inputs are
			registered and must meet setup and hold times.

5L, 3G	SBx	Input	Synchronous Byte Write Inputs: ªxº refers to the byte being written (byte
(a) (b)			a, b). SGW overrides SBx.

4E	SE1	Input	Synchronous Chip Enable: Active low to enable chip.
			Negated high Ð blocks ADSP or deselects chip when ADSC is
			asserted.

2B	SE2	Input	Synchronous Chip Enable: Active high for depth expansion.

6B	SE3	Input	Synchronous Chip Enable: Active low for depth expansion.

4H	SGW	Input	Synchronous Global Write: This signal writes all bytes regardless of the
			status of the SBx and SW signals. If only byte write signals SBx are
			being used, tie this pin high.

4M	SW	Input	Synchronous Write: This signal writes only those bytes that have been

			selected using the byte write SBx pins. If only byte write signals SBx
			are being used, tie this pin low.

4C, 2J, 4J, 6J, 4R	VDD	Supply	Core Power Supply.
1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U	VDDQ	Supply	I/O Power Supply.
3D, 5D, 3E, 5E, 3F, 5F, 5G, 3H, 5H,	VSS	Supply	Ground.
3K, 5K, 3L, 3M, 5M, 3N, 5N, 3P, 5P

1B, 7B, 1C, 7C, 2D, 4D, 7D, 1E, 6E,	NC	Ð	No Connection: There is no connection to the chip.
2F, 1G, 6G, 2H, 7H, 3J, 5J, 1K, 6K,
2L, 4L, 7L, 6M, 2N, 7N, 1P, 6P, 1R,
5R, 7R, 1T, 4T, 7T, 2U, 3U, 4U, 5U, 6U

MCM69P817	MOTOROLA FAST SRAM
4

TRUTH TABLE (See Notes 1 Through 5)

Address

Write 2, 4

Next Cycle

Used

SE1

SE2

SE3

ADSP

ADSC

ADV

DQx

Deselect

None

High±Z

Deselect

None

High±Z

Deselect

None

High±Z

Deselect

None

High±Z

Deselect

None

High±Z

Begin Read

External

High±Z

Begin Read

External

High±Z

Continue Read

High±Z

READ

Continue Read

READ

Continue Read

High±Z

READ

Continue Read

READ

Suspend Read

Current

High±Z

READ

Suspend Read

Current

READ

Suspend Read

Current

High±Z

READ

Suspend Read

Current

READ

Begin Write

External

High±Z

WRITE

Continue Write

High±Z

WRITE

Continue Write

High±Z

WRITE

Suspend Write

Current

High±Z

WRITE

Suspend Write

Current

High±Z

WRITE

NOTES:

1.X = don't care. 1 = logic high. 0 = logic low.

2.Write is defined as either (a) any SBx and SW low or (b) SGW is low.

3.G is an asynchronous signal and is not sampled by the clock K. G drives the bus immediately (tGLQX) following G going low.

4.On write cycles that follow read cycles, G must be negated prior to the start of the write cycle to ensure proper write data setup times. G must also remain negated at the completion of the write cycle to ensure proper write data hold times.

5.This read assumes the RAM was previously deselected.

LINEAR BURST ADDRESS TABLE (LBO = VSS)

1st Address (External)		2nd Address (Internal)		3rd Address (Internal)		4th Address (Internal)

X . . .	X00	X .	. . X01	X . . .	X10	X . . .	X11

X . . .	X01	X .	. . X10	X . . .	X11	X . . .	X00

X . . .	X10	X .	. . X11	X . . .	X00	X . . .	X01

X . . .	X11	X .	. . X00	X . . .	X01	X . . .	X10

INTERLEAVED BURST ADDRESS TABLE (LBO = VDD)

1st Address (External)		2nd Address (Internal)		3rd Address (Internal)		4th Address (Internal)

X . . .	X00	X . . .	X01	X . . .	X10	X . . .	X11

X . . .	X01	X . . .	X00	X . . .	X11	X . . .	X10

X . . .	X10	X . . .	X11	X . . .	X00	X . . .	X01

X . . .	X11	X . . .	X10	X . . .	X01	X . . .	X00

WRITE TRUTH TABLE

Cycle Type	SGW	SW	SBa	SBb

Read	H	H	X	X

Read	H	L	H	H

Write Byte a	H	L	L	H

Write Byte b	H	L	H	L

Write All Bytes	H	L	L	L

Write All Bytes	L	X	X	X

MOTOROLA FAST SRAM	MCM69P817
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