Motorola MCM6709RJ7R2, MCM6709RJ8R2, MCM6709RJ6, MCM6709RJ6R2, MCM6709RJ7 Datasheet

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Order this document by MCM6709R/D

64K x 4 Bit Static RAM

The MCM6709R is a 262,144 bit static random access memory organized as 65,536 words of 4 bits, fabricated using high±performance silicon±gate BiCMOS technology. Static design eliminates the need for external clocks or timing strobes.

Output enable (G) is a special control feature that provides increased system flexibility and eliminates bus contention problems.

The MCM6709R meets JEDEC standards and is available in a revolutionary pinout 300 mil, 28 lead plastic surface±mount SOJ package.

•Single 5 V ± 10% Power Supply

•Fully Static Ð No Clock or Timing Strobes Necessary

•All Inputs and Outputs are TTL Compatible

•Center Power and I/O Pins for Reduced Noise

•Three State Outputs

•Fast Access Times: MCM6709R±6 = 6 ns

		MCM6709R±7 = 7 ns
		MCM6709R±8 = 8 ns
		BLOCK DIAGRAM
A
A
A
A						MATRIX
A		ROW
						128 x 4
A				COLUMNS
A
A
A
DQ0				COLUMN I/O				•
								•
•	•	INPUT	COLUMN DECODER					•
•	•
•	•	DATA
		CONTROL
DQ3
		A	A	A	A	A	A	A
E
W
G

MCM6709R

J PACKAGE 300 MIL SOJ CASE 810B±03

PIN ASSIGNMENT

A0						1	28		A15
A1						2	27		A14
A2						3	26		A13
A3						4	25		A12
						5	24
		E							G
DQ0						6	23		DQ3
VCC						7	22		VSS
VSS						8	21		VCC
DQ1						9	20		DQ2
						10	19		A11
	W
A4						11	18		A10
A5						12	17		A9
A6						13	16		A8
A7						14	15		NC

PIN NAMES

A0 ± A15 . . . . . . . . . . . . Address Inputs

W . . . . . . . . . . . . . . . . . . . . Write Enable

G . . . . . . . . . . . . . . . . . . . Output Enable

E . . . . . . . . . . . . . . . . . . . . . . Chip Enable

DQ0 ± DQ3 . . . . . . . . Data Input/Output

VCC . . . . . . . . . . . . + 5 V Power Supply

VSS . . . . . . . . . . . . . . . . . . . . . . . Ground

NC . . . . . . . . . . . . . . . . . No Connection

All power supply and ground pins must be connected for proper operation of the device.

REV 1 5/95

Motorola, Inc. 1995

TRUTH TABLE (X = Don't Care)

	E			G		W			Mode	Output	Cycle
H				X			X		Not Selected	High±Z	Ð
	L			H			H		Read	High±Z	Ð
	L			L			H		Read	Dout	Read Cycle
	L			X			L		Write	Din	Write Cycle

ABSOLUTE MAXIMUM RATINGS (See Note)

Rating	Symbol	Value		Unit
Power Supply Voltage	VCC	± 0.5 to +	7.0	V
Voltage Relative to VSS for Any Pin	Vin, Vout	± 0.5 to VCC + 0.5		V
Except VCC
Output Current (per I/O)	Iout	± 30		mA
Power Dissipation	PD	2.0		W
Temperature Under Bias	Tbias	± 10 to +	85	°C
Operating Temperature	TA	0 to + 70		°C
Storage Temperature Ð Plastic	Tstg	± 55 to + 125		°C

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.

This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high±impedance circuit.

This BiCMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow of at least 500 linear feet per minute is maintained.

DC OPERATING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 V ± 10%, TA = 0 to 70°C, Unless Otherwise Noted)

RECOMMENDED OPERATING CONDITIONS

Parameter	Symbol	Min	Typ	Max	Unit
Supply Voltage (Operating Voltage Range)	VCC	4.5	5.0	5.5	V
Input High Voltage	VIH	2.2	Ð	VCC + 0.3*	V
Input Low Voltage	VIL	± 0.5**	Ð	0.8	V

*VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width ≤ 2.0 ns) or I ≤ 30.0 mA.

**VIL (min) = ± 0.5 V dc @ 30.0 mA; VIL (min) = ± 2.0 V ac (pulse width ≤ 2.0 ns) or I ≤ 30.0 mA.

DC CHARACTERISTICS

		Parameter	Symbol	Min	Max	Unit
Input Leakage Current (All Inputs, Vin = 0 to VCC)			Ilkg(I)	Ð	± 1.0	μA
		= VIH, Vout = 0 to VCC)	Ilkg(O)		± 1.0	μA
Output Leakage Current (E				Ð
Output High Voltage (IOH = ± 4.0 mA)			VOH	2.4	Ð	V
Output Low Voltage (IOL = 8.0 mA)			VOL	Ð	0.4	V

POWER SUPPLY CURRENTS

				Parameter	Symbol	MCM6709R±6	MCM6709R±7	MCM6709R±8	Unit	Notes
AC Active Supply Current (Iout = 0 mA,					ICCA	195	190	185	mA	1, 2, 3
	VCC = max, f = fmax)
				= VIH, VCC = max, f = fmax)	ISB1
AC Standby Current (E						85	80	75	mA	1, 2, 3
CMOS Standby Current (VCC = max, f = 0 MHz,					ISB2	20	20	20	mA
	E	≥ VCC ± 0.2 V, Vin ≤ VSS, or ≥ VCC ± 0.2 V)

NOTES:

1.Reference AC Operating Conditions and Characteristics for input and timing (VIH/VIL, tr/tf, pulse level 0 to 3 V, VIH = 3 V).

2.All addresses transition simultaneously low (LSB) and then high (MSB).

3.Data states are all zero.

MCM6709R	MOTOROLA FAST SRAM
2

CAPACITANCE (f = 1.0 MHz, dV = 3.0							V, TA = 25°C, Periodically Sampled Rather Than 100% Tested)
							Parameter	Symbol	Max	Unit
Address Input Capacitance								Cin	5	pF
Control Pin Input Capacitance								Cin	6	pF
	(E,		G, W)
Input/Output Capacitance								CI/O	6	pF

AC OPERATING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted)

Input Timing Measurement Reference Level . . . . . . . . . . . .	. . . 1.5	V	Output Timing Measurement Reference Level . . . . . .	. . . . . . . 1.5 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	0 to 3.0	V	Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	See Figure 1A
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 2 ns

READ CYCLES 1 AND 2 (See Notes 1 and 2)

		MCM6709R±6		MCM6709R±7		MCM6709R±8
Parameter	Symbol	Min	Max	Min	Max	Min	Max	Unit	Notes
Read Cycle Time	tAVAV	6	Ð	7	Ð	8	Ð	ns	3
Address Access Time	tAVQV	Ð	6	Ð	7	Ð	8	ns
Chip Enable Access Time	tELQV	Ð	6	Ð	7	Ð	8	ns
Output Enable Access Time	tGLQV	Ð	4	Ð	4	Ð	4	ns
Output Hold from Address Change	tAXQX	3	Ð	3	Ð	3	Ð	ns
Chip Enable Low to Output Active	tELQX	3	Ð	3	Ð	3	Ð	ns	4, 5, 6
Output Enable Low to Output Active	tGLQX	0	Ð	0	Ð	0	Ð	ns	4, 5, 6
Chip Enable High to Output High±Z	tEHQZ	0	3	0	3.5	0	4	ns	4, 5, 6
Output Enable High to Output High±Z	tGHQZ	0	3	0	3.5	0	4	ns	4, 5, 6
NOTES:

1.W is high for read cycle.

2.Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles.

3.All read cycle timings are referenced from the last valid address to the first transitioning address.

4.At any given voltage and temperature, tEHQZ max is less than tELQX min, and tGHQZ max is less than tGLQX min, both for a given device and from device to device.

5.Transition is measured 200 mV from steady±state voltage with load of Figure 1B.

6.This parameter is sampled and not 100% tested.

		AC TEST LOADS
				+5 V
	OUTPUT			480 Ω
			OUTPUT
	Z0 = 50 Ω	RL = 50 Ω
			255 Ω	5 pF
		VL = 1.5 V
	Figure 1A			Figure 1B

TIMING LIMITS

The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the system must supply at least that much time (even though most devices do not require it). On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never provides data later than that time.

MOTOROLA FAST SRAM	MCM6709R
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