Motorola MCM72PB8ML3.5, MCM72FB8ML8, MCM72FB8ML8R, MCM72FB8ML7.5R, MCM72PB8ML4R Datasheet

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INDICATION

(corner with (Drawings Not to Scale) fiducial)

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Order this document by MCM72FB8ML/D

Advance Information

256K x 72 Bit BurstRAM

Multichip Module

The 256K x 72 multichip module uses four 4M bit synchronous fast static RAMs designed to provide a burstable, high performance, secondary cache for the PowerPC and other high performance microprocessors. It is organized as 256K words of 72 bits each. This device integrates input registers, an output register (MCM72PB8ML only), a 2±bit address counter, and high speed SRAM onto a single monolithic circuit for reduced parts count in cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K). BiCMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability.

Addresses (SA), data inputs (DQx), and all control signals except output enable (G) and linear burst order (LBO) are clock (K) controlled through positive± edge±triggered noninverting registers.

Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst addresses can be generated internally (burst sequence operates in linear or interleaved mode dependent upon the state of LBO) and controlled by the burst address advance (ADV) input pin.

Write cycles are internally self±timed and are initiated by the rising edge of the clock (K) input. This feature eliminates complex off±chip write pulse generation and provides increased timing flexibility for incoming signals.

Synchronous byte write (SBx), synchronous global write (SGW), and synchronous write enable (SW) are provided to allow writes to either individual bytes or to all bytes. The eight bytes are designated as ªaº through ªhº. SBacontrols DQa, SBb controls DQb, etc. Individual bytes are written if the selected byte writes SBx are asserted with SW. All bytes are written if either SGW is asserted or if all SBx and SW are asserted.

The module can be configured as either a pipelined or flow±through SRAM. For read cycles, pipelined SRAMs output data is temporarily stored by an edge± triggered output register and then released to the output buffers at the next rising edge of clock (K). Flow±through SRAMs allow output to simply flow freely from the memory array.

The multichip module operates from a 3.3 V core power supply and all outputs operate on a separate 2.5 V or 3.3 V power supply. All inputs and outputs are JEDEC standard JESD8±5 compatible.

•3.3 V + 10%, ± 5% Core Power Supply, 2.5 V or 3.3 V I/O Supply

•ADSP, ADSC, and ADV Burst Control Pins

•Option for Pipeline or Flow±Through (Speeds Guaranteed When Module is Purchased by Appropriate Part Number)

•Selectable Burst Sequencing Order (Linear/Interleaved)

•Single±Cycle Deselect Timing

•Internally Self±Timed Write Cycle

•Byte Write and Global Write Control

•JEDEC BGA Pin Assignment

MCM72FB8ML

MCM72PB8ML

MULTICHIP MODULE

PBGA

CASE 1103B±01

PIN A1

INDICATION

(corner without

fiducial)

The PowerPC name is a trademark of IBM Corp., used under license therefrom.

This document contains information on a new product. Specifications and information herein are subject to change without notice.

REV 1 7/30/97

MOTOROLA FAST SRAM	MCM72FB8ML	MCM72PB8ML
Motorola, Inc. 1997
		1

Motorola MCM72PB8ML3.5, MCM72FB8ML8, MCM72FB8ML8R, MCM72FB8ML7.5R, MCM72PB8ML4R Datasheet

256K X 72 FOUR±CHIP MODULE BLOCK DIAGRAM

SA2 ± SA17

SA0

SA1

ADSP

ADSC

ADV

SE1

SE2

SE3

LBO

SGW

* Motorola TrueDie devices.

MCM69P/F819DC*

SA2 ± SA17

SA0

SA1

SBa

ADSP

DQ0 ± DQ8

DQa

ADSC

ADV

SBb

DQ9 ± DQ17

DQb

SE1

SE2

SE3

LBO

SGW

MCM69P/F819DC*

SA2 ± SA17

SA0

SA1

SBc

ADSP

DQ0 ± DQ8

DQc

ADSC

SBd

ADV

DQ9 ± DQ17

DQd

SE1

SE2

SE3

LBO

SGW

MCM69P/F819DC*

SA2 ± SA17

SA0

SA1

SBe

ADSP

DQ0 ± DQ8

DQe

ADSC

SBf

ADV

DQ9 ± DQ17

DQf

SE1

SE2

SE3

LBO

SGW

MCM69P/F819DC*

SA2 ± SA17

SA0

SA1

SBg

ADSP

DQ0 ± DQ8

DQg

ADSC

SBh

ADV

DQ9 ± DQ17

DQh

SE1

SE2

SE3

LBO

SGW

MCM72FB8ML MCM72PB8ML	MOTOROLA FAST SRAM
2

PIN ASSIGNMENT

5	6	7	8	9	10	11	12	13	14	15
A	DQe	SA	SA	SA	SE1	SA	SA	SA	DQd	DQd
DQe
B	DQe	SA	SA	SA	G	SA	SA	SA	DQd	DQd
DQe
C			VDDQ VDDQ			VDDQ	VDDQ	SE3
DQe	DQe	SE2			SGW				DQd	DQd
D		VDDQ	VDD	VSS		VSS	VDD	VDDQ	DQd
DQe	DQe				ADV					DQd
E						VSS	VDD		DQc
DQe	DQf	VDDQ	VDD	VSS	ADSC			VDDQ		DQd
F		VDDQ	VDD	VSS	ADSP	VSS	VDD	VDDQ	DQc
DQf	DQf									DQc
G				VSS		VSS	VDD	VDDQ	DQc
DQf	DQf	VDDQ	VDD		VSS					DQc
H		VDDQ	VSS	VSS	VSS	VSS	VSS	VDDQ
DQf	DQf								DQc	DQc
J			VSS	VSS	VSS	VSS	VSS
DQf	DQf	SBe						SBd	DQc	DQc
K			VSS	VSS	VSS	VSS	VSS
SBf	SBg	NC						NC	SBb	SBc
L			VSS	VSS	VSS	VSS	VSS
DQg	DQg	SBh						SBa	DQb	DQb
M		VDDQ VSS		VSS		VSS		VDDQ
DQg	DQg				VSS		VSS		DQb	DQb
N		VDDQ VDD		VSS	VSS	VSS	VDD	VDDQ
DQg	DQg								DQb	DQb
P		VDDQ VDD		VSS		VSS	VDD	VDDQ DQb
DQg	DQg				NC					DQb
R	DQh	VDDQ VDD		VSS	K	VSS	VDD	VDDQ DQa
DQg										DQb
T	DQh	VDDQ	VDD	VSS	SW	VSS	VDD
DQh								VDDQ DQa		DQa
U		LBO	VDDQ VDDQ		SA1	VDDQ	VDDQ	FT
DQh	DQh								DQa	DQa
V							SA
DQh	DQh	NC	SA	SA	SA0	SA		NC	DQa	DQa
W	DQh	NC	NC	NC	NC	NC	NC	NC	DQa	DQa
DQh

TOP VIEW

256K X 72 JEDEC FOUR±CHIP MODULE

209 BUMP PBGA

Not to Scale

MOTOROLA FAST SRAM	MCM72FB8ML MCM72PB8ML
	3

PIN DESCRIPTIONS

	Pin Locations	Symbol	Type	Description

	E10	ADSC	Input	Synchronous Address Status Controller: Active low, interrupts any
				ongoing burst and latches a new external address. Used to initiate
				READ, WRITE, or chip deselect cycle.

	F10	ADSP	Input	Synchronous Address Status Processor: Active low, interrupts any
				ongoing burst and latches a new external address. Used to initiate
				READ, WRITE, or chip deselect cycle (exception Ð chip deselect
				does not occur when ADSP is asserted and SE1 is high).

	D10	ADV	Input	Synchronous Address Advance: Increments address count in
				accordance with counter type selected (linear/interleaved).

(a)	R14, T14, T15, U14, U15, V14, V15,	DQx	I/O	Synchronous Data I/O: ªxº refers to the byte being read or written
	W14, W15			(byte a, b, c, d, e, f, g, h).
(b)	L14, L15, M14, M15, N14, N15, P14,
	P15, R15
(c)	E14, F14, F15, G14, G15, H14, H15,
	J14, J15
(d)	A14, A15, B14, B15, C14, C15, D14,
	D15, E15
(e)	A5, A6, B5, B6, C5, C6, D5, D6, E5
(f)	E6, F5, F6, G5, G6, H5, H6, J5, J6
(g)	L5, L6, M5, M6, N5, N6, P5, P6, R5
(h)	R6, T5, T6, U5, U6, V5, V6, W5, W6

	U13	FT	Input	Flow±Through Input: This pin must remain in steady state (this
				signal is not registered or latched). It must be tied high or low.
				Low Ð flow±through mode.
				High Ð pipeline mode.

	B10	G	Input	Asynchronous Output Enable.

	R10	K	Input	Clock: This signal registers the address, data in, and all control
				signals except G, LBO, and FT.

	U7	LBO	Input	Linear Burst Order Input: This pin must remain in steady state (this
				signal not registered or latched). It must be tied high or low.
				Low Ð linear burst counter (68K/PowerPC).
				High Ð interleaved burst counter (486/i960/Pentium).

	U10, V10	SA1, SA0	Input	Synchronous Address Inputs: These pins must be wired to the two
				LSBs of the address bus for proper burst operation. These inputs
				are registered and must meet setup and hold times.

A7, A8, A9, A11, A12, A13, B7, B8, B9,		SA2 ± SA17	Input	Synchronous Address Inputs: These inputs are registered and must
	B11, B12, B13, V8, V9, V11, V12			meet setup and hold times.

	L13, K14, K15, J13, J7, K5, K6, L7	SBx	Input	Synchronous Byte Write Inputs: ªxº refers to the byte being written

	(a) (b) (c) (d) (e) (f) (g) (h)			(byte a, b, c, d, e, f, g, h). SGW overrides SBx.

	A10	SE1	Input	Synchronous Chip Enable: Active low to enable chip.

				Negated high±blocks ADSP or deselects chip when ADSC is
				asserted.

	C7	SE2	Input	Synchronous Chip Enable: Active high for depth expansion.

	C13	SE3	Input	Synchronous Chip Enable: Active low for depth expansion.

	C10	SGW	Input	Synchronous Global Write: This signal writes all bytes regardless of
				the status of the SBx and SW signals. If only byte write signals SBx
				are being used, tie this pin high.

	T10	SW	Input	Synchronous Write: This signal writes only those bytes that have
				been selected using the byte write SBx pins. If only byte write
				signals SBx are being used, tie this pin low.

	D8, D12, E8, E12, F8, F12, G8,	VDD	Supply	Core Power Supply.
G12, N8, N12, P8, P12, R8, R12, T8, T12

	C8, C9, C11, C12, D7, D13, E7,	VDDQ	Supply	I/O Power Supply.
	E13, F7, F13, G7, G13, H7, H13,
	M7, M13, N7, N13, P7, P13, R7,
	R13, T7, T13, U8, U9, U11, U12

MCM72FB8ML MCM72PB8ML	MOTOROLA FAST SRAM
4

PIN DESCRIPTIONS (continued)

Pin Locations

Symbol

Type

Description

D9, D11, E9, E11, F9, F11, G9 ± G11,

VSS

Supply

Ground.

H8 ± H12, J8 ± J12, K8 ± K12, L8 ± L12,

M8 ± M12, N9 ± N11, P9, P11, R9, R11,

T9, T11

K7, K13, P10, V7, V13, W7 ± W13

No Connection: There is no connection to the chip.

TRUTH TABLE (See Notes 1 through 5)

Address

Write 2, 4

Next Cycle

Used

SE1

SE2

SE3

ADSP

ADSC

ADV

DQx

Deselect

None

High±Z

Deselect

None

High±Z

Deselect

None

High±Z

Deselect

None

High±Z

Deselect

None

High±Z

Begin Read

External

High±Z

Begin Read

External

High±Z

Continue Read

High±Z

READ

Continue Read

READ

Continue Read

High±Z

READ

Continue Read

READ

Suspend Read

Current

High±Z

READ

Suspend Read

Current

READ

Suspend Read

Current

High±Z

READ

Suspend Read

Current

READ

Begin Write

External

High±Z

WRITE

Continue Write

High±Z

WRITE

Continue Write

High±Z

WRITE

Suspend Write

Current

High±Z

WRITE

Suspend Write

Current

High±Z

WRITE

NOTES:

1.X = Don't Care. 1 = logic high. 0 = logic low.

2.Write is defined as either 1) any SBx and SW low or 2) SGW is low.

3.G is an asynchronous signal and is not sampled by the clock K. G drives the bus immediately (tGLQX) following G going low.

4.On write cycles that follow read cycles, G must be negated prior to the start of the write cycle to ensure proper write data setup times. G must also remain negated at the completion of the write cycle to ensure proper write data hold times.

5.This read assumes the RAM was previously deselected.

LINEAR BURST ADDRESS TABLE (LBO = VSS)

1st Address (External)		2nd Address (Internal)		3rd Address (Internal)		4th Address (Internal)

X . . .	X00	X . . .	X01	X . . .	X10	X . . .	X11

X . . .	X01	X . . .	X10	X . . .	X11	X . . .	X00

X . . .	X10	X . . .	X11	X . . .	X00	X . . .	X01

X . . .	X11	X . . .	X00	X . . .	X01	X . . .	X10

INTERLEAVED BURST ADDRESS TABLE (LBO = VDD)

1st Address (External)		2nd Address (Internal)		3rd Address (Internal)		4th Address (Internal)

X . . .	X00	X . . .	X01	X . . .	X10	X . . .	X11

X . . .	X01	X . . .	X00	X . . .	X11	X . . .	X10

X . . .	X10	X . . .	X11	X . . .	X00	X . . .	X01

X . . .	X11	X . . .	X10	X . . .	X01	X . . .	X00

MOTOROLA FAST SRAM	MCM72FB8ML MCM72PB8ML
	5

WRITE TRUTH TABLE

Cycle Type	SGW	SW	SBa	SBb	SBc	SBd	SBe	SBf	SBg	SBh

Read	H	H	X	X	X	X	X	X	X	X

Read	H	L	L	H	H	H	H	H	H	H

Write Byte a	H	L	L	H	H	H	H	H	H	H

Write Byte b	H	L	H	L	H	H	H	H	H	H

Write Byte c	H	L	H	H	L	H	H	H	H	H

Write Byte d	H	L	H	H	H	L	H	H	H	H

Write Byte e	H	L	H	H	H	H	L	H	H	H

Write Byte f	H	L	H	H	H	H	H	L	H	H

Write Byte g	H	L	H	H	H	H	H	H	L	H

Write Byte h	H	L	H	H	H	H	H	H	H	L

Write All Bytes	H	L	L	L	L	L	L	L	L	L

Write All Bytes	L	X	X	X	X	X	X	X	X	X

ABSOLUTE MAXIMUM RATINGS (See Note 1)

Rating	Symbol	Value	Unit	Notes

Power Supply Voltage	VDD	VSS ± 0.5 to + 4.6	V
I/O Supply Voltage	VDDQ	VSS ± 0.5 to VDD	V	2
Input Voltage Relative to VSS for	Vin, Vout	VSS ± 0.5 to	V	2
Any Pin Except VDD		VDD + 0.5
Input Voltage (Three±State I/O)	VIT	VSS ± 0.5 to	V	2
		VDDQ + 0.5
Output Current (per I/O)	Iout	± 20	mA
Package Power Dissipation	PD	6.4	W	3
Ambient Temperature	TA	0 to 70	°C
Die Temperature	TJ	110	°C	3
Temperature Under Bias	Tbias	± 10 to 85	°C
Storage Temperature	Tstg	± 55 to 125	°C
NOTES:

1.Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPER-

ATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.

2.This is a steady±state DC parameter that is in effect after the power supply has achieved its nominal operating level. Power sequencing is not necessary.

3.Power dissipation capability is dependent upon package characteristics and use environment. See Package Thermal Characteristics.

PACKAGE THERMAL CHARACTERISTICS

This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high±impedance circuit.

Thermal Resistance		Symbol	Max	Unit	Notes

Junction to Ambient (@ 200 lfm)	Single±Layer Board	RθJA	19	°C/W	1, 2
	Four±Layer Board		13

Junction to Board (Bottom)		RθJB	10	°C/W	3
Junction to Case (Top)		RθJC	0.3	°C/W	4

NOTES:

1.Junction temperature is a function of on±chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, board population, and board thermal resistance.

2.Per SEMI G38±87.

3.Indicates the average thermal resistance between the die and the printed circuit board.

4.Indicates the average thermal resistance between the die and the case top surface via the cold plate method (MIL SPEC±883 Method 1012.1).

MCM72FB8ML MCM72PB8ML	MOTOROLA FAST SRAM
6

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