MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document by MCM69P536C/D
32K x 36 Bit Pipelined BurstRAM
Synchronous Fast Static RAM
The MCM69P536C is a 1M±bit synchronous fast static RAM designed to provide a burstable, high performance, secondary cache for the 68K Family, PowerPC , 486, i960 , and Pentium microprocessors. It is organized as 32K words of 36 bits each. This device integrates input registers, an output register, a 2±bit address counter, and high speed SRAM onto a single monolithic circuit for reduced parts count in cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K). BiCMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability.
Addresses (SA), data inputs (DQx), and all control signals except output enable (G) and Linear Burst Order (LBO) are clock (K) controlled through positive±edge±triggered noninverting registers.
Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst addresses can be generated internally by the MCM69P536C (burst sequence operates in linear or interleaved mode dependent upon the state of LBO) and controlled by the burst address advance (ADV) input pin.
Write cycles are internally self±timed and are initiated by the rising edge of the clock (K) input. This feature eliminates complex off±chip write pulse generation and provides increased timing flexibility for incoming signals.
Synchronous byte write (SBx), synchronous global write (SGW), and synchronous write enable SW are provided to allow writes to either individual bytes or to all bytes. The four bytes are designated as ªaº, ªbº, ªcº, and ªdº. SBa controls DQa, SBb controls DQb, etc. Individual bytes are written if the selected
byte writes SBx are asserted with SW. All bytes are written if either SGW is asserted or if all SBx and SW are asserted.
For read cycles, pipelined SRAMs output data is temporarily stored by an edge±triggered output register and then released to the output buffers at the next rising edge of clock (K).
The MCM69P536C operates from a 3.3 V power supply and all inputs and outputs are LVTTL compatible.
•MCM69P536C±4 = 4 ns Access / 7.5 ns Cycle MCM69P536C±4.5 = 4.5 ns Access / 8 ns Cycle MCM69P536C±5 = 5 ns Access / 10 ns Cycle MCM69P536C±6 = 6 ns Access / 12 ns Cycle MCM69P536C±7 = 7 ns Access / 13.3 ns Cycle
•Single 3.3 V + 10%, ± 5% Power Supply
•ADSP, ADSC, and ADV Burst Control Pins
•Selectable Burst Sequencing Order (Linear/Interleaved)
•Internally Self±Timed Write Cycle
•Byte Write and Global Write Control
•5 V Tolerant on all Pins (Inputs and I/Os)
•100±Pin TQFP Package
MCM69P536C
TQ PACKAGE
TQFP
CASE 983A±01
The PowerPC name is a trademark of IBM Corp., used under license therefrom. i960 and Pentium are trademarks of Intel Corp.
REV 3 2/9/98
MOTOROLA FAST SRAM |
MCM69P536C |
Motorola, Inc. 1998 |
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1 |
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FUNCTIONAL BLOCK DIAGRAM |
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LBO |
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ADV |
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K |
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BURST |
2 |
15 |
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ADSC |
K2 |
COUNTER |
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CLR |
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ADSP |
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2 |
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SA |
ADDRESS |
15 |
13 |
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SA1 |
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REGISTER |
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SA0 |
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SGW |
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SW |
WRITE |
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REGISTER |
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SBa |
a |
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WRITE |
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REGISTER |
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SBb |
b |
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4 |
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WRITE |
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REGISTER |
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K |
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c |
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SBc |
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WRITE |
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REGISTER |
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SBd |
d |
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K2 |
K |
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SE1 |
ENABLE |
ENABLE |
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SE2 |
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REGISTER |
REGISTER |
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SE3 |
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32K x 36 ARRAY
36 36
DATA±IN DATA±OUT
REGISTER REGISTER
G
DQa ± DQd
MCM69P536C |
MOTOROLA FAST SRAM |
2 |
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PIN ASSIGNMENT
SA SA SE1 SE2 |
SBd SBc |
SBb SBa |
SE3 |
V |
V K |
SGW SW G |
ADSC |
ADSP ADV SA SA |
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DD |
SS |
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100 99 98 97 96 |
95 94 93 92 91 |
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90 89 |
88 87 86 85 84 83 82 81 |
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DQc |
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1 |
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80 |
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DQb |
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DQc |
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2 |
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79 |
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DQb |
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DQc |
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3 |
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78 |
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DQb |
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VDD |
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4 |
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77 |
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V |
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VSS |
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5 |
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DD |
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76 |
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VSS |
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DQc |
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6 |
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75 |
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DQb |
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DQc |
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7 |
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74 |
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DQb |
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DQc |
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8 |
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73 |
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DQb |
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DQc |
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9 |
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72 |
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DQb |
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VSS |
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10 |
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71 |
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VSS |
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VDD |
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11 |
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70 |
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VDD |
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DQc |
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12 |
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69 |
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DQb |
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DQc |
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13 |
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68 |
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DQb |
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14 |
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NC |
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67 |
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VSS |
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VDD |
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15 |
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66 |
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NC |
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NC |
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16 |
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65 |
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VDD |
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VSS |
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17 |
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64 |
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NC |
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DQd |
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18 |
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63 |
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DQa |
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DQd |
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19 |
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62 |
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DQa |
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VDD |
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20 |
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61 |
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VDD |
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VSS |
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21 |
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60 |
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VSS |
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DQd |
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22 |
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59 |
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DQa |
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DQd |
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23 |
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58 |
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DQa |
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DQd |
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24 |
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57 |
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DQa |
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DQd |
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25 |
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56 |
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DQa |
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VSS |
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26 |
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55 |
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VSS |
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VDD |
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27 |
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54 |
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DQd |
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28 |
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DD |
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53 |
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DQa |
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DQd |
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29 |
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52 |
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DQd |
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51 |
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31 32 33 34 35 36 37 38 39 40 41 42 |
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43 44 45 46 47 48 49 |
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50 |
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LBO SA SA SA SA |
SA1 SA0 NC NC V |
V NC |
NC SA SA SA SA SA NC |
NC |
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SS |
DD |
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MOTOROLA FAST SRAM |
MCM69P536C |
|
3 |
PIN DESCRIPTIONS
Pin Locations |
Symbol |
Type |
Description |
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85 |
ADSC |
Input |
Synchronous Address Status Controller: Initiates READ, WRITE, or |
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chip deselect cycle. |
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84 |
ADSP |
Input |
Synchronous Address Status Processor: Initiates READ, WRITE, or |
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chip deselect cycle (exception Ð chip deselect does not occur when |
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ADSP is asserted and SE1 is high). |
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83 |
ADV |
Input |
Synchronous Address Advance: Increments address count in |
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accordance with counter type selected (linear/interleaved). |
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(a) 51, 52, 53, 56, 57, 58, 59, 62, 63 |
DQx |
I/O |
Synchronous Data I/O: ªxº refers to the byte being read or written |
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(b) 68, 69, 72, 73, 74, 75, 78, 79, 80 |
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(byte a, b, c, d). |
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(c) 1, 2, 3, 6, 7, 8, 9, 12, 13 |
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(d) 18, 19, 22, 23, 24, 25, 28, 29, 30 |
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86 |
G |
Input |
Asynchronous Output Enable Input: |
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Low Ð enables output buffers (DQx pins). |
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High Ð DQx pins are high impedance. |
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89 |
K |
Input |
Clock: This signal registers the address, data in, and all control signals |
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except G and LBO. |
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31 |
LBO |
Input |
Linear Burst Order Input: This pin must remain in steady state (this |
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signal not registered or latched). It must be tied high or low. |
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Low Ð linear burst counter (68K/PowerPC). |
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High Ð interleaved burst counter (486/i960/Pentium). |
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32, 33, 34, 35, 44, 45, 46, |
SA |
Input |
Synchronous Address Inputs: These inputs are registered and must |
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47, 48, 81, 82, 99, 100 |
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meet setup and hold times. |
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36, 37 |
SA1,SA0 |
Input |
Synchronous Address Inputs: These pins must be wired to the two |
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LSBs of the address bus for proper burst operation. These inputs are |
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registered and must meet setup and hold times. |
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93, 94, 95, 96 |
SBx |
Input |
Synchronous Byte Write Inputs: ªxº refers to the byte being written (byte |
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(a) (b) (c) (d) |
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a, b, c, d). SGW overrides SBx. |
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98 |
SE1 |
Input |
Synchronous Chip Enable: Active low to enable chip. |
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Negated high±blocks ADSP or deselects chip when ADSC is asserted. |
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97 |
SE2 |
Input |
Synchronous Chip Enable: Active high for depth expansion. |
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92 |
SE3 |
Input |
Synchronous Chip Enable: Active low for depth expansion. |
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88 |
SGW |
Input |
Synchronous Global Write: This signal writes all bytes regardless of the |
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status of the SBx and SW signals. If only byte write signals SBx are |
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being used, tie this pin high. |
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87 |
SW |
Input |
Synchronous Write: This signal writes only those bytes that have been |
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selected using the byte write SBx pins. If only byte write signals SBx |
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are being used, tie this pin low. |
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4, 11, 15, 20, 27, 41, 54, |
VDD |
Supply |
Power Supply: 3.3 V + 10%, ± 5%. |
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61, 65, 70, 77, 91 |
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5, 10, 17, 21, 26, 40, 55, |
VSS |
Supply |
Ground. |
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60, 67, 71, 76, 90 |
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64 |
NC |
Input |
No Connection: There is no connection to the chip. For compatibility |
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|
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reasons, it is recommended that this pin be tied low for system designs |
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that do not have a sleep mode associated with the cache/memory |
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|
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controller. Other vendors' RAMs may have implemented the Sleep |
||||
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Mode (ZZ) feature. |
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||||
14, 16, 38, 39, 42, 43, 49, 50, 66 |
NC |
Ð |
No Connection: There is no connection to the chip. |
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|
MCM69P536C |
MOTOROLA FAST SRAM |
4 |
|