Motorola MCM63P736TQ100R, MCM63P818ZP66, MCM63P818ZP66R, MCM63P736ZP100R, MCM63P736ZP133 Datasheet

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Order this document by MCM63P736/D

Product Preview

128K x 36 and 256K x 18 Bit

Pipelined BurstRAM

Synchronous Fast Static RAM

The MCM63P736 and MCM63P818 are 4M bit synchronous fast static RAMs designed to provide a burstable, high performance, secondary cache for the PowerPC and other high performance microprocessors. The MCM63P736 is organized as 128K words of 36 bits each and the MCM63P818 is organized as 256K words of 18 bits each. These devices integrate input registers, an output register, a 2±bit address counter, and high speed SRAM onto a single monolithic circuit for reduced parts count in cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K).

Addresses (SA), data inputs (DQx), and all control signals except output enable (G), sleep mode (ZZ), and linear burst order (LBO) are clock (K) controlled through positive±edge±triggered noninverting registers.

Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst addresses can be generated internally by the MCM63P736 and MCM63P818 (burst sequence operates in linear or interleaved mode dependent upon the state of LBO) and controlled by the burst address advance (ADV) input pin.

Write cycles are internally self±timed and are initiated by the rising edge of the clock (K) input. This feature eliminates complex off±chip write pulse generation and provides increased timing flexibility for incoming signals.

Synchronous byte write (SBx), synchronous global write (SGW), and synchronous write enable (SW) are provided to allow writes to either individual bytes or to all bytes. The bytes are designated as ªaº, ªbº, etc. SBacontrols DQa, SBb controls DQb, etc. Individual bytes are written if the selected byte writes SBx are as- serted with SW. All bytes are written if either SGW is asserted or if all SBx and SW are asserted.

For read cycles, pipelined SRAMs output data is temporarily stored by an edge±triggered output register and then released to the output buffers at the next rising edge of clock (K).

The MCM63P736 and MCM63P818 operate from a 3.3 V core power supply and all outputs operate on a 2.5 V or 3.3 V power supply. All inputs and outputs are JEDEC standard JESD8±5 compatible.

•MCM63P736/MCM63P818±133 = 4 ns Access/7.5 ns Cycle (133 MHz) MCM63P736/MCM63P818±100 = 5 ns Access/10 ns Cycle (100 MHz) MCM63P736/MCM63P818±66 = 7 ns Access/15 ns Cycle (66 MHz)

•3.3 V + 10%, ± 5% Core Power Supply, 2.5 V or 3.3 V I/O Supply

•ADSP, ADSC, and ADV Burst Control Pins

•Selectable Burst Sequencing Order (Linear/Interleaved)

•Two±Cycle Deselect Timing

•Internally Self±Timed Write Cycle

•Byte Write and Global Write Control

•Sleep Mode (ZZ)

•PB1 Version 2.0 Compatible

•JEDEC Standard 119±Pin PBGA and 100±Pin TQFP Packages

The PowerPC name is a trademark of IBM Corp., used under license therefrom.

MCM63P736

MCM63P818

TQ PACKAGE

TQFP

CASE 983A±01

ZP PACKAGE

PBGA

CASE 999±01

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.

10/8/97

MOTOROLA FAST SRAM	MCM63P736 MCM63P818
Motorola, Inc. 1997	•
	1

	FUNCTIONAL BLOCK DIAGRAM
LBO
ADV
K		BURST		2	17/18
ADSC	K2	COUNTER			128K x 36 /
					256K x 18
		CLR
ADSP					ARRAY
			2
SA	ADDRESS	17/18	15/16
SA1
	REGISTER
SA0
SGW
SW	WRITE				36/18	36/18
	REGISTER
SBa	a
	WRITE
	REGISTER
SBb	b
					4/2
	WRITE				DATA±IN	DATA±OUT
					REGISTER	REGISTER
	REGISTER
					K
	c*
SBc*
	WRITE
	REGISTER
SBd*	d*
			K		WRITE
	K2	K
				REGISTER
SE1	ENABLE	ENABLE
SE2
	REGISTER	REGISTER
SE3
G						DQa ± DQd /
ZZ						DQa ± DQb

* Valid only for MCM63P736.

MCM63P736•MCM63P818	MOTOROLA FAST SRAM
2

MCM63P736 PIN ASSIGNMENTS

1	2	3	4	5	6	7
A						VDDQ
VDDQ	SA	SA	ADSP	SA	SA
B	SE2	SA	ADSC	SA	SE3	NC
NC
C	SA	SA	VDD	SA	SA	NC
NC
D		VSS		VSS		DQb
DQc	DQc		NC		DQb
E						DQb
DQc	DQc	VSS	SE1	VSS	DQb
F		VSS		VSS	DQb	VDDQ
VDDQ	DQc		G
G			ADV	SBb	DQb	DQb
DQc	DQc	SBc
H		VSS		VSS	DQb	DQb
DQc	DQc		SGW
J	VDD		VDD		VDD	VDDQ
VDDQ		NC		NC
K						DQa
DQd	DQd	VSS	K	VSS	DQa
L			NC			DQa
DQd	DQd	SBd		SBa	DQa
M			SW	VSS		VDDQ
VDDQ	DQd	VSS			DQa
N		VSS		VSS		DQa
DQd	DQd		SA1		DQa
P		VSS		VSS
DQd	DQd		SA0		DQa	DQa
R	SA	LBO	VDD	NC	SA	NC
NC
T						ZZ
NC	NC	SA	SA	SA	NC
U	NC	NC	NC	NC	NC	VDDQ
VDDQ

SA SA SE1 SE2 SBd

SBc SBb SBa SE3

V

V K

SGW SW

G

ADSC

ADSP ADV SA SA

DD

SS

DQc		100 99 9897 9695 94 93 92 91 90 89 88 87 86 85 84 83 82 81
		1																							80													DQb
DQc
		2																							79													DQb
DQc
		3																							78													DQb
VDDQ		4																							77													VDDQ
VSS		5																							76													VSS
DQc		6																							75													DQb
DQc
		7																							74													DQb
DQc
		8																							73													DQb
DQc
		9																							72													DQb
VSS		10
																									71													VSS
VDDQ		11																							70													VDDQ
DQc		12																							69													DQb
DQc		13																							68													DQb
		14
NC																									67													VSS
VDD		15																							66													NC
NC		16																							65													VDD
VSS		17																							64													ZZ
DQd		18																							63													DQa
DQd
		19																							62													DQa
VDDQ
		20																							61													V
VSS		21																																				DDQ
																									60													V
DQd		22																																				SS
																									59													DQa
DQd
		23																							58													DQa
DQd		24
																									57													DQa
DQd		25																							56													DQa
VSS
		26																							55													VSS
VDDQ		27																							54													VDDQ
DQd		28																							53													DQa
DQd		29																							52													DQa
		30
DQd																									51													DQa
		31 32 33 34 35 36 3738 39 40 41 42 43 444546 4748 49 50
			LBO SA SA SA SA SA1 SA0														NC NC V					V			NC NC SA SA SA SA SA SA SA
																					SS	DD

TOP VIEW 119 BUMP PBGA

TOP VIEW 100 PIN TQFP

Not to Scale

MOTOROLA FAST SRAM	MCM63P736•MCM63P818
	3

MCM63P736 PBGA PIN DESCRIPTIONS

Pin Locations	Symbol	Type			Description
4B	ADSC	Input	Synchronous Address Status Controller: Active low, interrupts any
			ongoing burst and latches a new external address. Used to initiate a
			READ, WRITE, or chip deselect.
4A	ADSP	Input	Synchronous Address Status Processor: Active low, interrupts any
			ongoing burst and latches a new external address. Used to initiate a
			new READ or chip deselect (exception Ð chip deselect does not occur
			when ADSP is asserted and SE1 is high).
4G	ADV	Input	Synchronous Address Advance: Increments address count in
			accordance with counter type selected (linear/interleaved).
(a) 6K, 7K, 6L, 7L, 6M, 6N, 7N, 6P, 7P	DQx	I/O	Synchronous Data I/O: ªxº refers to the byte being read or written
(b) 6D, 7D, 6E, 7E, 6F, 6G, 7G, 6H, 7H			(byte a, b, c, d).
(c) 1D, 2D, 1E, 2E, 2F, 1G, 2G, 1H, 2H
(d) 1K, 2K, 1L, 2L, 2M, 1N, 2N, 1P, 2P
4F	G	Input	Asynchronous Output Enable Input:
			Low Ð enables output buffers (DQx pins).
			High Ð DQx pins are high impedance.
4K	K	Input	Clock: This signal registers the address, data in, and all control signals
			except G, LBO, and ZZ.
3R	LBO	Input	Linear Burst Order Input: This pin must remain in steady state (this
			signal not registered or latched). It must be tied high or low.
			Low Ð linear burst counter (68K/PowerPC).
			High Ð interleaved burst counter (486/i960/Pentium).
2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C,	SA	Input	Synchronous Address Inputs: These inputs are registered and must
5C, 6C, 2R, 6R, 3T, 4T, 5T			meet setup and hold times.
4N, 4P	SA1, SA0	Input	Synchronous Address Inputs: These pins must be wired to the two
			LSBs of the address bus for proper burst operation. These inputs are
			registered and must meet setup and hold times.
5L, 5G, 3G, 3L	SBx	Input	Synchronous Byte Write Inputs: ªxº refers to the byte being written (byte
(a) (b) (c) (d)			a, b, c, d). SGW overrides SBx.
4E	SE1	Input	Synchronous Chip Enable: Active low to enable chip.
			Negated high Ð blocks ADSP or deselects chip when ADSC is
			asserted.
2B	SE2	Input	Synchronous Chip Enable: Active high for depth expansion.
6B	SE3	Input	Synchronous Chip Enable: Active low for depth expansion.
4H	SGW	Input	Synchronous Global Write: This signal writes all bytes regardless of the
			status of the SBx and SW signals. If only byte write signals SBx are
			being used, tie this pin high.
4M	SW	Input	Synchronous Write: This signal writes only those bytes that have been
			selected using the byte write SBx pins. If only byte write signals SBx
			are being used, tie this pin low.
7T	ZZ	Input	Sleep Mode: This active high asynchronous signal places the RAM into
			the lowest power mode. The ZZ pin disables the RAMs internal clock
			when placed in this mode. When ZZ is negated, the RAM remains in
			low power mode until it is commanded to READ or WRITE. Data
			integrity is maintained upon returning to normal operation.
4C, 2J, 4J, 6J, 4R	VDD	Supply	Core Power Supply.
1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U	VDDQ	Supply	I/O Power Supply.
3D, 5D, 3E, 5E, 3F, 5F, 3H, 5H,	VSS	Supply	Ground.
3K, 5K, 3M, 5M, 3N, 5N, 3P, 5P
1B, 7B, 1C, 7C, 4D, 3J, 5J, 4L, 1R, 5R,	NC	Ð	No Connection: There is no connection to the chip.
7R, 1T, 2T, 6T, 2U, 3U, 4U, 5U, 6U

MCM63P736•MCM63P818	MOTOROLA FAST SRAM
4

MCM63P736 TQFP PIN DESCRIPTIONS

Pin Locations	Symbol	Type			Description
85	ADSC	Input	Synchronous Address Status Controller: Active low, interrupts any
			ongoing burst and latches a new external address. Used to initiate a
			READ, WRITE, or chip deselect.
84	ADSP	Input	Synchronous Address Status Processor: Active low, interrupts any
			ongoing burst and latches a new external address. Used to initiate a
			new READ or chip deselect (exception Ð chip deselect does not occur
			when ADSP is asserted and SE1 is high).
83	ADV	Input	Synchronous Address Advance: Increments address count in
			accordance with counter type selected (linear/interleaved).
(a) 51, 52, 53, 56, 57, 58, 59, 62, 63	DQx	I/O	Synchronous Data I/O: ªxº refers to the byte being read or written
(b) 68, 69, 72, 73, 74, 75, 78, 79, 80			(byte a, b, c, d).
(c) 1, 2, 3, 6, 7, 8, 9, 12, 13
(d) 18, 19, 22, 23, 24, 25, 28, 29, 30
86	G	Input	Asynchronous Output Enable Input:
			Low Ð enables output buffers (DQx pins).
			High Ð DQx pins are high impedance.
89	K	Input	Clock: This signal registers the address, data in, and all control signals
			except G, LBO, and ZZ.
31	LBO	Input	Linear Burst Order Input: This pin must remain in steady state (this
			signal not registered or latched). It must be tied high or low.
			Low Ð linear burst counter (68K/PowerPC).
			High Ð interleaved burst counter (486/i960/Pentium).
32, 33, 34, 35, 44, 45, 46,	SA	Input	Synchronous Address Inputs: These inputs are registered and must
47, 48, 49, 50, 81, 82, 99, 100			meet setup and hold times.
36, 37	SA1, SA0	Input	Synchronous Address Inputs: these pins must be wired to the two LSBs
			of the address bus for proper burst operation. These inputs are
			registered and must meet setup and hold times.
93, 94, 95, 96	SBx	Input	Synchronous Byte Write Inputs: ªxº refers to the byte being written (byte
(a) (b) (c) (d)			a, b, c, d). SGW overrides SBx.
98	SE1	Input	Synchronous Chip Enable: Active low to enable chip.
			Negated high Ð blocks ADSP or deselects chip when ADSC is
			asserted.
97	SE2	Input	Synchronous Chip Enable: Active high for depth expansion.
92	SE3	Input	Synchronous Chip Enable: Active low for depth expansion.
88	SGW	Input	Synchronous Global Write: This signal writes all bytes regardless of the
			status of the SBx and SW signals. If only byte write signals SBx are
			being used, tie this pin high.
87	SW	Input	Synchronous Write: This signal writes only those bytes that have been
			selected using the byte write SBx pins. If only byte write signals SBx
			are being used, tie this pin low.
64	ZZ	Input	Sleep Mode: This active high asynchronous signal places the RAM into
			the lowest power mode. The ZZ pin disables the RAMs internal clock
			when placed in this mode. When ZZ is negated, the RAM remains in
			low power mode until it is commanded to READ or WRITE. Data
			integrity is maintained upon returning to normal operation.
15, 41, 65, 91	VDD	Supply	Core Power Supply.
4, 11, 20, 27, 54, 61, 70, 77	VDDQ	Supply	I/O Power Supply.
5, 10, 17, 21, 26, 40,	VSS	Supply	Ground.
55, 60, 67, 71, 76, 90
14, 16, 38, 39, 42, 43, 66	NC	Ð	No Connection: There is no connection to the chip.

MOTOROLA FAST SRAM	MCM63P736•MCM63P818
	5

MCM63P818 PIN ASSIGNMENTS

1	2	3	4	5	6	7
A	SA	SA		SA	SA	VDDQ
VDDQ			ADSP
B	SE2	SA	ADSC	SA	SE3	NC
NC
C	SA	SA	VDD	SA	SA	NC
NC
D		VSS		VSS		NC
DQb	NC		NC		DQa
E
NC	DQb	VSS	SE1	VSS	NC	DQa
F		VSS		VSS	DQa	VDDQ
VDDQ	NC		G
G			ADV	VSS	NC
NC	DQb	SBb				DQa
H		VSS		VSS
DQb	NC		SGW		DQa	NC
J	VDD		VDD		VDD	VDDQ
VDDQ		NC		NC
K		VSS		VSS
NC	DQb		K		NC	DQa
L		VSS	NC
DQb	NC			SBa	DQa	NC
M			SW	VSS		VDDQ
VDDQ	DQb	VSS			NC
N		VSS		VSS		NC
DQb	NC		SA1		DQa
P		VSS		VSS
NC	DQb		SA0		NC	DQa
R	SA	LBO	VDD	NC	SA	NC
NC
T	SA	SA		SA	SA	ZZ
NC			NC
U					NC	VDDQ
VDDQ	NC	NC	NC	NC

SA SA SE1 SE2 NC

NC SBb SBa SE3

V

V K

SGW SW G

ADSC

ADSP ADV SA SA

DD

SS

NC		100 99 9897 9695 94 93 92 91 90 89 88 87 86 85 84 83 82 81
		1																							80													SA
NC
		2																							79													NC
NC
		3																							78													NC
VDDQ		4																							77													VDDQ
VSS		5																							76													VSS
NC		6																							75													NC
NC
		7																							74													DQa
DQb
		8																							73													DQa
DQb
		9																							72													DQa
VSS		10
																									71													VSS
VDDQ		11																							70													VDDQ
DQb		12																							69													DQa
DQb		13																							68													DQa
		14
NC																									67													VSS
VDD		15																							66													NC
NC		16																							65													VDD
VSS		17																							64													ZZ
DQb		18																							63													DQa
DQb
		19																							62													DQa
VDDQ
		20																							61													V
VSS		21																																				DDQ
																									60													V
DQb		22																																				SS
																									59													DQa
DQb
		23																							58													DQa
DQb		24
																									57													NC
NC		25																							56													N
V
		26																																				V
SS																									55													CSS
VDDQ		27																							54													VDDQ
NC		28																							53													NC
NC		29																							52													NC
		30
NC																									51													NC
		31 32 33 34 35 36 3738 39 40 41 42 43 444546 4748 49 50
			LBO SA SA SA SA SA1 SA0														NC NC V					V			NC NC SA SA SA SA SA SA SA
																					SS	DD

TOP VIEW 119 BUMP PBGA

TOP VIEW 100 PIN TQFP

Not to Scale

MCM63P736•MCM63P818	MOTOROLA FAST SRAM
6